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Forum Post: RE: Storing config of a cell in a file/cellview
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Forum Post: RE: DRC error on regulator output
Have you tried setting the pin type to "POWER" (and visible)? POWER to POWER is acceptable. Output to POWER should cause a DRC since any general output should not be tied directly to a power rail. You can also silence the OUTPUT error or set the DRC level down to a warning by adjusting the DRC settings.
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Forum Post: RE: Storing config of a cell in a file/cellview
The other thing you can also do with the Variables and Parameters assistant is save sets of variable/parameter values (or sweeps) to a "setup state". That's the box and icons at the top of the image that Quek shared. Then it's easy to switch back and forth between fixed global variables and sweeps, or to enable certain combinations. Also the parameters can easily be set up to be matched parameters between a group of devices (without having to put variables on everything), or you can setup "ratio" parameters (such as when you've got a value with is N times another and you want to maintain that ratio whilst sweeping the unit value). If it was just a matter of recording a set of variables, then of course you could do that with ADE L - you just need to save the state and just save the variables. However, the problem with that is that you need to modify the schematic to reference all these global variables, which is awkward and hard to maintain. As Quek said, the parameterisation capability in ADE XL (and ADE Explorer and Assembler in IC617) means you don't have to edit the schematic at all; you can override values without actually modifying the schematic at all. Once you're happy with a result, you can backannotate the values onto the actual schematic (i.e. update the schematic to reflect the values you're happy with). Regards, Andrew
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Forum Post: RE: Problem saving intrinsic parameters using save statement save NM0:all
When you use save NM0. nm_hp :all the nm_np has to refer to the instance name within the subckt not the subckt name. So you need to look in the definition of nm_hp and see what the instance name is called, and use that. The error message clearly says there is no instance called nm_hp. Why is it the instance name? Well, there could be multiple instances of devices within the subckt - it needs to know which instance you're talking about. Regards, Andrew.
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Forum Post: RE: when is .cdsinit.local loaded?
There is nothing in virtuoso that loads a file called ".cdsinit.local". All that happens is that virtuoso looks for a file called ".cdsinit" (in various places; the order of which can be overridden with the Cadence Search File mechanism, if you desire) and then loads the first one it finds. Often CAD groups customise the .cdsinit so that it loads other files; in your case it appears that it looks for and loads a file called ".cdsinit.local". The order in which it does that is completely determined by however that CAD team has written the SKILL code in their .cdsinit. I cannot answer this generally, because it depends on the specifics of that implementation. You should contact your own CAD team to find out how they've done it and what controls they provide (if any) for changing the order of when this customer-specific file gets loaded. Regards, Andrew.
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Forum Post: RE: Calibre LVS errors for a design generated in Encounter
Thank you Kari I would like to know how to check if all std cells pins are connected, how to do that ? I think connectivity violations check doesn't check power/ground connections of std cells, does it ?
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Forum Post: How to make an ideal diode model for diode from analogLib?
I am trying to make a model and use it for ideal diode from analogLib library. However, I don't know how to modify the built-in potential (or forward voltage) of the diode. I tried to add VJ variable and set it to a small value like 0.1V. However, from I-V characteristic of simulation, it doesn't seem to have any effect on forward voltage at all. The built-in potential from the simulation is about 650mV. Can anybody tell me how to do that? I want the diode is like ideal (zero forward voltage and infinite slope). Here is the model file I used (diode.scs): simulator lang=spice .model schottky D (LEVEL = 3 IS=1p RS=0 BV=40.0 IBV=1p VJ=0.1 CJO=0 M=0.5 N=1 TT=0 )
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Forum Post: RE: Align pins based on connectivity
Hi Ramakrishnan You can do it as follows using the "Pin Placer" function: a. Switch to layoutXL using "Launch->Layout XL" b. Ensure that there are flight lines linking the top level pins to the pins of the instance c. Go to "Place->Pin Placement" d. Use "Level-1 pin" as the edge attribute Please search for "Placing a Pin on a Lower-level Instance Terminal" in $CDSHOME/doc/fphelp/fphelp.pdf. Best regards Quek
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Forum Post: RE: SKILL descend into a component sub-circuit schematic
Hi Aleksandr Perhaps you are looking for "dbGetAnyInstSwitchMaster"? Please refer to $CDSHOME/doc/skdfref/skdfref.pdf. You can actually just use dbOpenCellViewByType repeatedly too. E.g. if you know that the instances are all using "schematic" views, you can just use this: subCell=dbOpenCellViewByType(inst~>libName inst~>cellName "schematic" "" "a") It is a very simple method and works well most of the time because most people use "schematic" and "layout" as the actual view names. Once you have obtained the subCell ID using either dbGetAnyInstSwitchMaster or dbOpenCellViewByType, you can repeat the process of dbFindAnyInstByName and then modify the parameters using "instID~>param=123". Best regards Quek
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Forum Post: RE: SKILL descend into a component sub-circuit schematic
Hi Quek, Thanks for the reply. I'll look up the "dbGetAnyInstSwitchMaster", but if repetitive "dbOpenCellViewByType" works as well, I'd rather use that. Thanks, Aleksandr
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Forum Post: QRC extraction problem
Hi all: I'm at QRC stage now where I have encountered this extraction problem: Cadence Extraction QRC - 64-bit Parasitic Extractor - Version 13.2.0-s451 Tue Jul 22 19:35:08 PDT 2014 ----------------------------------------------------------------------------------------------------------- Copyright 2013 Cadence Design Systems, Inc. INFO (EXTQRCXOPT-243) : For Assura inputs, if the "output_setup -directory_name" option was not specified, it is automatically set to the input directory. WARNING (LBRCXM-624): Warning [input]: Line 8: 'well' statement is ignored in ICT file line. WARNING (LBRCXM-624): Warning [input]: Line 10: 'well' statement is ignored in ICT file line. INFO (LBRCXM-624): No temperature processing will occur for the layer CONT, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer CONT, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer VIA1, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer VIA2, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer VIA3, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer VIA4, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer VIAF, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer VIAF, because this layerhas no Tc1 and Tc2. INFO (LBRCXU-108): Starting /opt/cadence/installs/ASSURA41/tools.lnx86/assura/bin/rcxToDfII /home/cds/ee642_project_umais/d1/__qrc.rcx_cmd -t -f /home/cds/ee642_project_umais/d1/extview.tmp -w /home/cds/ee642_project_umais/d1 -cdslib /home/cds/ee642_project_umais/cds.lib Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.05s. @(#)$CDS: rcxToDfII_64 version av4.1:Production:dfII6.1.6-64b:IC6.1.6-64b.101 08/06/2013 14:01 (sjfnl785) $ sub-version 4.1_USR4, integ signature 2013-08-06-1301 run on cdspc from /opt/cadence/installs/ASSURA41/tools.lnx86/assura/bin/64bit/rcxToDfII on Sun Mar 12 10:42:10 2017 *WARNING* Technology must be specified! *LF-INFO* Loading cmos150/cmos150.skill/cmos150_cdfCbks.il done *LF-INFO* cmos150 libInit.il loaded successfully. *LF-INFO* Loading cmos150hv/cmos150hv.skill/cmos150hv_cdfCbks.il done *LF-INFO* cmos150hv libInit.il loaded successfully. *ERROR* No library model for device "nmosld40v_4 auLvs cmos150hv". *WARNING* (DB-270211): dbOpenCellViewByType: Failed to open cellview (nmosld40v_4 auLvs) from lib (cmos150hv) in 'r' mode because cellview does not exist, or cellview type is not recognized by dbOpenCellViewByType. *WARNING* (DB-220704): The Pcell super master: cmos150/break/auLvs is not a SKILL super master. The usage of non-SKILL Pcells in Virtuoso is not a supported feature. *WARNING* (DB-220704): The Pcell super master: cmos150/make/auLvs is not a SKILL super master. The usage of non-SKILL Pcells in Virtuoso is not a supported feature. ERROR: Assura is terminating because some library models do not exist. Your rules and your dfII model libraries are inconsistent. Assura requires all library models in the rule file be present in the database when running rcx with the "extracted_view" option. INFO (LBRCXU-111): Warning /opt/cadence/installs/ASSURA41/tools.lnx86/assura/bin/rcxToDfII exit with bad status INFO (LBRCXU-112): Warning Status 256 INFO (LBRCXU-113): Warning QRC execution terminated ***** aveng fork terminated abnormally ***** If anyone has fixed such an error or knows how please help
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Forum Post: RE: How to make an ideal diode model for diode from analogLib?
The diode model is not intended to be used as an "ideal" diode, so I don't think that's you're best starting point. Note - this comes with a bit of caution; modelling "ideal" components is often not a good idea in circuit simulators because they're really not intended for that. For a start, an infinite slope could lead to convergence problems. You could implement it with a relay in spectre: subckt idealDiode (a c) // note, the on resistance shouldn't be below 1mOhm D1 (a c a c) relay rclosed=1m vt1=0.0 vt2=1m ends idealDiode Note that it would not be a good idea to reduce the closed resistance (on resistance) below about 1mOhm; this can lead to convergence problems. You also have to have some small region for the transition - but hopefully this is good enough (with 1mOhm on resistance the current gets up to kA pretty quickly!). Then you can use this component: Dideal (n1 n2) idealDiode Regards, Regards, Andrew.
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Forum Post: RE: QRC extraction problem
Turn this switch off on the QRC form: The default behaviour is that it checks that all devices referenced in the QRC setup can be found, regardless of whether they are used in your layout. With this turned off, it doesn't do that. Andrew.
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Forum Post: RE: QRC extraction problem
Thanks Andrew I have done this. Now there comes another error: ------- Cadence Extraction QRC - 64-bit Parasitic Extractor - Version 13.2.0-s451 Tue Jul 22 19:35:08 PDT 2014 ----------------------------------------------------------------------------------------------------------- Copyright 2013 Cadence Design Systems, Inc. INFO (EXTQRCXOPT-243) : For Assura inputs, if the "output_setup -directory_name" option was not specified, it is automatically set to the input directory. WARNING (LBRCXM-624): Warning [input]: Line 8: 'well' statement is ignored in ICT file line. WARNING (LBRCXM-624): Warning [input]: Line 10: 'well' statement is ignored in ICT file line. INFO (LBRCXM-624): No temperature processing will occur for the layer CONT, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer CONT, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer VIA1, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer VIA2, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer VIA3, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer VIA4, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer VIAF, because this layerhas no Tc1 and Tc2. INFO (LBRCXM-624): No temperature processing will occur for the layer VIAF, because this layerhas no Tc1 and Tc2. INFO (LBRCXU-108): Starting /opt/cadence/installs/ASSURA41/tools.lnx86/assura/bin/rcxToDfII /home/cds/ee642_project_umais/monticelli1986testing2.3startupcombinedbhybrid1lfv2bsingcurvepush13.56MHz/__qrc.rcx_cmd -t -f /home/cds/ee642_project_umais/monticelli1986testing2.3startupcombinedbhybrid1lfv2bsingcurvepush13.56MHz/extview.tmp -w /home/cds/ee642_project_umais/monticelli1986testing2.3startupcombinedbhybrid1lfv2bsingcurvepush13.56MHz -cdslib /home/cds/ee642_project_umais/cds.lib Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.04s. @(#)$CDS: rcxToDfII_64 version av4.1:Production:dfII6.1.6-64b:IC6.1.6-64b.101 08/06/2013 14:01 (sjfnl785) $ sub-version 4.1_USR4, integ signature 2013-08-06-1301 run on cdspc from /opt/cadence/installs/ASSURA41/tools.lnx86/assura/bin/64bit/rcxToDfII on Sun Mar 12 11:54:48 2017 *WARNING* Technology must be specified! *LF-INFO* Loading cmos150/cmos150.skill/cmos150_cdfCbks.il done *LF-INFO* cmos150 libInit.il loaded successfully. INFO (LBRCXU-114): Finished /opt/cadence/installs/ASSURA41/tools.lnx86/assura/bin/rcxToDfII INFO (LBRCXM-642): Constructing the RCX run script /opt/cadence/installs/EXT132/tools.lnx86/extraction/bin/64bit//capgen: error while loading shared libraries: libtermcap.so.2: cannot open shared object file: No such file or directory INFO (RCXSPIC-27150): The following forked command failed. Contact Cadence Customer Support for assistance. /opt/cadence/installs/EXT132/tools.lnx86/extraction/bin/64bit//capgen -techdir /opt/PDK/PDK_LF15Ai_V0_5_0/pv/qrc/6metal/typ -lvs /home/cds/ee642_project_umais/monticelli1986testing2.3startupcombinedbhybrid1lfv2bsingcurvepush13.56MHz.xcn -p2lvs /opt/PDK/PDK_LF15Ai_V0_5_0/pv/qrc/6metal/typ/qrcTechFile -reseqn -sw3d -blocking _ngate_cap_m_bulk:0.1,STI,DIFF,POLY2 -blocking _ngate_cap_m_dnw:0.1,STI,DIFF,POLY2 -blocking _pgate_cap_m:0.1,STI,DIFF,POLY2 -blocking _ngate_cap_l_bulk:0.1,STI,DIFF,POLY2 -blocking _ngate_cap_l_dnw:0.1,STI,DIFF,POLY2 -blocking _ngate_cap_h_bulk:0.1,STI,DIFF,POLY2 -blocking _ngate_cap_h_dnw:0.1,STI,DIFF,POLY2 -blocking mim1c:0.6,STI,METAL5,METALF -p POLY2,allGate,DIFF -length_units meters -genericMos _nmos_ll_sal1,D,G,S -genericMos _nmos_3_sal,D,G,S -genericMos _nmos_5_sal,D,G,S -genericMos _pmos_ll_sal1,D,G,S -genericMos _pmos_3_sal,D,G,S -genericMos _pmos_5_sal,D,G,S /home/cds/ee642_project_umais/monticelli1986testing2.3startupcombinedbhybrid1lfv2bsingcurvepush13.56MHz Forking: /opt/cadence/installs/EXT132/tools.lnx86/extraction/bin/64bit//capgen -techdir /opt/PDK/PDK_LF15Ai_V0_5_0/pv/qrc/6metal/typ -lvs /home/cds/ee642_project_umais/monticelli1986testing2.3startupcombinedbhybrid1lfv2bsingcurvepush13.56MHz.xcn -p2lvs /opt/PDK/PDK_LF15Ai_V0_5_0/pv/qrc/6metal/typ/qrcTechFile -reseqn -sw3d -blocking _ngate_cap_m_bulk:0.1,STI,DIFF,POLY2 -blocking _ngate_cap_m_dnw:0.1,STI,DIFF,POLY2 -blocking _pgate_cap_m:0.1,STI,DIFF,POLY2 -blocking _ngate_cap_l_bulk:0.1,STI,DIFF,POLY2 -blocking _ngate_cap_l_dnw:0.1,STI,DIFF,POLY2 -blocking _ngate_cap_h_bulk:0.1,STI,DIFF,POLY2 -blocking _ngate_cap_h_dnw:0.1,STI,DIFF,POLY2 -blocking mim1c:0.6,STI,METAL5,METALF -p POLY2,allGate,DIFF -length_units meters -genericMos _nmos_ll_sal1,D,G,S -genericMos _nmos_3_sal,D,G,S -genericMos _nmos_5_sal,D,G,S -genericMos _pmos_ll_sal1,D,G,S -genericMos _pmos_3_sal,D,G,S -genericMos _pmos_5_sal,D,G,S /home/cds/ee642_project_umais/monticelli1986testing2.3startupcombinedbhybrid1lfv2bsingcurvepush13.56MHz ERROR (LBRCXM-644): Bad return status from RCX script generator. 0x100 INFO (LBRCXM-709): ***** QRC terminated abnormally ***** ---- I have libtermcap.so.2 file in /lib/libtermcap.so.2 /lib64/libtermcap.so.2 But when I try to open the file it says: "This link cannot be used because its target “/lib64/libncurses.so.5.9” doesn't exist" Please let me know any suggestions to resolve this issue. Thanks in Advance. Umais
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Forum Post: RE: QRC extraction problem
Umais, I'm not sure what you mean "when I try to open the file". Open with what? I'd check what "ls -l /lib64/libtermcap.so.2" shows, and also "ls -lL /lib64/libtermcap.so.2". These libraries should come from the "compat-libtermcap" rpm, and the libncurses should come from the "ncurses-libs" rpm. I'd make sure that you have both installed. Looking at various QRC versions, EXT152 and later doesn't seem to require libtermcap.so.2 but does require libncurses (for capgen, at least). You can always check shared library bindings with: ldd /cds/lnx86/EXT151_latest/tools/extraction/bin/64bit/capgen and similar for the path to whichever you're using. Regards, Andrew.
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Forum Post: RE: How to make an ideal diode model for diode from analogLib?
Thank you, Andrew Beckett! You are right I tried some ideal components before and faced convergence problem. For the diode, I don't need it to be perfectly idea but something close to that. However, as in the picture above, the forward voltage is too large and the slope is not that steep. I am trying to follow your method but I get stuck. You helped me with one similar example before as here . This example is a bit different to me. I created a model file named idealDiode.scs with content: subckt idealDiode (a c) // note, the on resistance shouldn't be below 1mOhm D1 (a c a c) relay rclosed=1m vt1=0.0 vt2=1m Then created a diode symbol with two pins a, c and name as "idealDiode". And then do the all the things as the given link above. however, where should I put this line "Dideal (n1 n2) idealDiode"?
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Forum Post: how to prevent highlight done by highlight_timing_report
Hi, Tool: Innovus When a new highlight_timing_report command is issued, the previous highlight is automatically de-highlighted. I want to keep previous highlight and "add" new highlights. Please suggest if it is possible.
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Forum Post: RE: when is .cdsinit.local loaded?
Thanks Andew! Indeed this is customized settings from the CAD team, where loading .cdsinit.local file is defined in .cdsinit It seems that .cdsinit is the only place to define any customized settings, is this correct? Does cadence also try to load some other files? I remember that Cadence searches a few paths for .cdsinit file before starts, does it load the first one it finds? what if I have two .cdsinit file located at different locations, and they differ in content, will both .cdsinit file be loaded?
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Forum Post: iPad files manager
you can retrieve data by yourself. There are programs to do that. For example Ipad Manager I used it few times. it's free and it works as good as can be expected. The main thing is to stop using the external hard disk until you use this tool, and avoid writing any files to it.Good luck!
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Forum Post: Dimming on layout window any given area?
Hi Andrew, Thanks actively helping us. I have question like this, we can do "dimming" on layout windows, through display options. We can do dimming based for conditions ie scope. However is there any chance for dimming on layout window with given list of coordinates? Example, I would like to dimm the layout window from (X1,Y1) to (X2,Y2). Layout should be in read mode and nothing is selected. Regards, Venkatraman
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