Yass, OK, you didn't mention that rather important detail. The problem is not the foreach at all, it's the fact that the list() function has too many arguments - it would fail on that. Having a long list in itself isn't an issue, but trying to build it with a single call to the list() function with over 260,000 arguments is going to be a problem. If instead it was a quoted list: Volt = '( "/I1/Vp" "/I2/Vp" "/I3/Vp" ..... "I262144/Vp") then it would have been fine. Of course, if the names are incrementing, this is a bit pointless - generating it with code makes far more sense. Andrew
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Forum Post: RE: buildString using a ForLoop to load and delete data on the fly
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Forum Post: Use instance name for design variable in schematic
I have an array of 64x64 components in a schematic and I would like to make a few design variables for some of the CDF parameters of said components but I dont want to go through 4096 one by one. Is ther a way to use the instance name for a variable? I tried VAR() but coud not get it to work.
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Forum Post: RE: SNR calculation wrong by 3 dB?
Dear Fede26 and bernd2700, You piqued my interest with your initial question Fede26 (as it did with you bernd2700 I guess too!) and provided some motivation to better understand the difference you observed in Cadence Spectrum Assistant and your expected results. I am pretty sure I can explain the difference and have put together a test case, run a series of simulations and done some post-processing using both Cadence tools as well as my own tools. I am just documenting the results and will post them in the next day for your consideration. I believe part of the issue, although not the entire issue, is the application that I believe the Spectrum Assistant was designed for - ADCs and its terminology and requirements. I'm including a few words about that too in the notes. I beg your patience as I assemble the document! Shawn
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Forum Post: Z-Axis delay feedback and Package Pin Delay supported in OrCAD PCB Designer Professional?
I've been playing with the Z-Axis delay feedback and Package Pin Delay features in OrCAD PCB Designer Professional 17.4-2019 S024 [12/6/2021] and they seem to be supported. Is that correct? I just want to be 100% sure they are supported since I've seen features comparisons that indicates otherwise. /F
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Forum Post: RE: Full contact via holes not shown in 3D
This is a known issue which has been reported to Cadence to fix. Maybe raise this with Cadence / Channel Partner as well. The only option you have is to change it from full copper to a thermal relief
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Forum Post: RE: Z-Axis delay feedback and Package Pin Delay supported in OrCAD PCB Designer Professional?
Yes they are fully supported in OrCAD Prodfessional 17.4-2019. Just make sure you turn on the Analysis modes in CM - Analysis - Electrical.
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Forum Post: RE: QRC Configuration options in PVS
Dear Andrew, I am grateful to you for your clear answer and help support, You made it clear for me, so I will contact my foundry tech team to add these configuration setting into my PVS setting Thank you once again Best Regards
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Forum Post: RE: How to create layout labels automatically
Dear Andrew, Thank you very much for your response, I have turned off the visibility of CETEXT that I used for the label, and as you can see from the image below there is no label on the screen If I do the label manually from Create>Label, the label looks fine as shown below if again I turn the CETEXT visibility off for this one, the label will be fine there as you see from the image below I have tried to repeat your suggestion but using different layer for labeling as allowed by my technology, but again I have the same reported issue Thank you once again for your help Best Regards
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Forum Post: RE: How to create layout labels automatically
I checked in the same sub-version you're using and it works fine for me - the only time it doesn't happen is if the pin is already placed in the layout (in which case no new pin is created anyway), or if I turn off the "Create Label" checkbox. I suggest you contact customer support . We'll need to see what exactly you're doing to determine what's going wrong. Andrew
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Forum Post: RE: Which takes priority?
This is down to the Constraint Object Hierarchy, basically Region wins in this case. The hierarchy is documented in "Working with Constraints" in the Online help, and in the Constraint Manager User Guide available from the Cadence Support site.
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Forum Post: RE: How to obtain Discrete-Time (DT) response from a switched-cap (SC) circuit (integrator)?
Dear Frank, Yes, obviously I have a lack of understanding the PAC, and as a consequence, you unfortunately have to tell me: “I already have written you this and that”. But, believe me, it is NOT because I haven’t read all your messages carefully! So, I dare to summarize what you have said so far in my own words now, how I can imagine the PAC sampled is working. Please have a look: If I want to know what is the output amplitude at e.g. 4559 Hz for testcase A) ( = the circuit with the “Ideal S&H” only), I simply inject a sinusoid of only this frequency, run a transient analysis (with setting “maxstep” equal “1/maxacfreq”) until to be in steady-state condition. Then basically should I have the same accuracy as the PAC receives, correct? Subsequently, over the Cadence calculator’s function “sample”, I sample the output with my PSS fundamental frequency with 1kHz e.g. on every rising edge of the PSS clock source “V0”, and then measure the amplitude result by doing “(max-min)/2”. Correct? Then, I think, I have fulfilled your statements: I sample only once per fundamental PSS period, just at the right edge (to also have the phase correct), and I will get aliased components as well. ==> What is NOT clear to me, is the following: This “(max-min)/2” takes place in Time-Domain (TD). But you also write “ The sampled PAC analysis only looks at the output at the input frequency ”. So how the PAC can distinguish this, if something comes from an aliased frequency or not, if the operation is done in TD?? And obviously, I got the results of -0.19 dB (so the straight 0 dB line) by doing “(max-min)/2” for the “PAC sampled, rising EDGE ”, to be more precisely. ==> How can I imagine then / what does PAC internally do, in order to get from this “edge” to the “time averaged” option? I do not have to run it again, but only select this option of the already calculated results. Why I am asking this? Because without having understood how the PAC works, I think, it will be hard to find a valid procedure, that will then produce the same (or at least similar + understood limitations) results as the PAC itself. At the end, I want to tell my AC analysis over MT: “Please give me the equivalent result of PAC sampled rising edge” or “now please for time averaged”. Of course, for every DUT, exactly the same procedure shall hold true (Not: For circuit A do zero-stuffing, for circuit B another thing to get the same results as PAC). I have the feeling that I am near, but not still there: I could reproduce all the PAC results of all the 3 test-circuits (DUTs), but I had to apply different procedures (1x DFT + zero-stuffing, and 1x DFT without it, to be equivalent to the “PAC sampled rising edge”). Many thanks, bernd2700
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Forum Post: Sigrity - Tip of the Week: How to fix overlapping zones during translation
While translating the Rigid-Flex multizone design, zones may slightly overlap each other at the boundaries. You can fix this by enabling the Fix shape overlapping between zone shapes option. Go to Tools > Options > Edit Options > Layout > Translator > RigidFlex > Multizone options This option is available from Sigrity 2022.1 base version. Team SimTech Cadence Design Systems
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Forum Post: RE: How to obtain Discrete-Time (DT) response from a switched-cap (SC) circuit (integrator)?
[quote userid="538772" url="~/cadence_technology_forums/f/custom-ic-design/51410/how-to-obtain-discrete-time-dt-response-from-a-switched-cap-sc-circuit-integrator/1383449#1383449"]But you also write “ The sampled PAC analysis only looks at the output at the input frequency ”. So how the PAC can distinguish this, if something comes from an aliased frequency or not, if the operation is done in TD??[/quote] More precisely, I should probably have said: "With maxsideband=0, the sampled PAC analysis interprets the output as a signal at the input frequency and also plots it at this frequency." Actually, the sampled PAC analysis does not run an additional time-domain simulation but uses the internal results of the time-domain PSS analysis. [quote userid="538772" url="~/cadence_technology_forums/f/custom-ic-design/51410/how-to-obtain-discrete-time-dt-response-from-a-switched-cap-sc-circuit-integrator/1383449#1383449"]How can I imagine then / what does PAC internally do, in order to get from this “edge” to the “time averaged” option? I do not have to run it again, but only select this option of the already calculated results.[/quote] When I look at the directory where Spectre saves its simulation results, I can see that when I run a sampled PAC analysis, Spectre also generates all the files for a normal PAC analysis. Probably, the corresponding calculations are either a prerequisite for the sampled PAC analysis or don't cause much additional computational effort (maybe Andrew or someone else from Cadence can comment on this). Fundamentally, however, normal PAC and sampled PAC are different analysis types and there is no direct way to generate one result from the other.
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Forum Post: RE: Which takes priority?
I was just wanting confirmation that 2 overlapping regions with different constraints would revert to the smallest setting if a larger setting region is overlapping the smaller on part of its area (shapes are rectangles and could overlap in a corner etc)
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Forum Post: Generate layout from symbols with design variables
I created some schematic symbols which have some design variables (channel length pPar("L"), channel width pPar("W") ) of the MOSFETs being used inside the symbol). But when I generated a layout from this symbol (at a higher level schematic) through the "connectivity" in Virtuoso XL. The pcells could not shown correctly message ("Pcell Eval failed"). I have already set the parameter values of the symbols in the higher level scheamtic. But it seems that the parameter values could not be passed to the MOSFET devices inside the symbol during the layout generation. What should I do?
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Forum Post: RE: Generate layout from symbols with design variables
From what you've described, this should work. There must be some detail that's is hard to guess that's wrong - so please contact customer support . Regards, Andrew
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Forum Post: Matched group - Analyze choses wrong pin pair target
I have a matched group that seems to chose the wrong target pin pair when running the Analyze command. Is there a reason for not choosing the longest trace (DQ21)? See below screen capture. By the way, how is the Delay column calculated? /F
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Forum Post: RE: How to change VIVA zoom time-axis (Shift+ mouse scroll)
Thank you very much Shawn! I tried your suggestion but still I am not able to control the X-Zoom in Viva (Please see the attached screenshot). I am using Exceed TurboX, and I believe there is an issue with it when I use the (Shift-Mouse Wheel) combination. This is why I was looking to change the bindkey. Mouse-Right-Click zoom method still works though as illustrated in your video. Kindest Regards, Nader Fathy
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Forum Post: RE: Full contact via holes not shown in 3D
You should try changing it from full copper to a thermal relief. cookie clicker
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Forum Post: Assembler: possible to re-evaluate only results yielding "eval err" right after simulation?
Hi! Is it possible to somehow make Assembler re-evaluate only the results that yield "eval err" right after simulation? Context: I have a testbench that calculates several expressions, all of which evaluate correctly right after simulation, except for a couple, which however evaluate correctly after pressing the "Re-calculate results" button in "Full recalculation" mode (the "Incremental recalculation" mode has no effect). Unfortunately, this re-calculation mode becomes impractical when the number of results and points is too high (e.g. 4h to re-evaluate a 400-point sweep, which is way more than the actual simulation itself takes!). In this particular case, all the outputs that yield "eval err" right after simulation call a skill procedure which I load from my .cdsinit, but for some reason Assembler "doesn't know" during its initial results evaluation. For example, these are the errors I get in the exprOutputs.log for each of these outputs that call the "calibrated_reconstruction()" procedure: \e *Error* ("eval" 0 t nil ("*Error* eval: undefined function" calibrated_reconstruction)) \e \e \o [2022-05-25 04:25:16.473 +0200] [error] - point:'1' test:'config_misc_minimal' \o Expression:'car((calibrated_reconstruction VT("/sADC_Dscaled") (vOUTdiff / VAR("TB__vREFdiff")) VAR("MEAS__TRAN__TstartSED") VAR("MEAS__TRAN__TstopSED") VAR("TB__CLOCK__Tperiod") VAR("SIM__TRAN__Npoints") 10.0 0.01 VAR("TB__REC__Niterations") 1 VAR("TB__REC__FlagVerbose")))' \o because of the following error(s) \o *Error* eval: undefined function [Attributes] {"point": 1, "testname": "config_misc_minimal", "?test": "config_misc_minimal", "?expression": "vOUTdiff__at_SED__ENOB"} ...alternatively, would there be a way to somehow "register" my procedure to make Assembler "know it" during its initial results evaluation? Thanks in advance for any help! KR, Jorge.
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