Since your VSS and V_input_low are both zero, VSS related power will be zero.
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Forum Post: RE: Cadence Liberate Characterization Help
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Forum Post: RE: Cadence Liberate Characterization Help
Hi, yes it is clear to me why the VSS pg power became 0. No issue of that The question I have is, as per my characterization library content (take a look at it : https://pastebin.com/grfasa1s ), even the leakage values I got for VDD pg_pin are wrong. i.e. leakage_power ( ) { value : 0.0484719 ; when : "I&!ZN" ; related_pg_pin : VDD; } leakage_power ( ) { value : 0.141881 ; when : "!I&ZN" ; related_pg_pin : VDD; } But when I simulate this inverter schematic with parasitics in AE, the observed leakage power (IDDxVDD) when the input=1 (PMOS off) was 95.95 pW (87pA*1.1V). When the input=0 (NMOS off), this was found to be 190.01 pW (172.74 pA * 1.1V). I used both internal and external (spectre) simulators for characterization (same PVT in both cases), but the result is same. Can anyone explain why the spice simulation values differ from the characterization result. Thanks Anuradha
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Forum Post: Problem changing the net name of a pin through a script.
Hi all, I am very new to skill coding and made this basic script to make the pin name and terminal name lowercase: selected = geGetSelSet() foreach(rectpin selected rectpin~>pin~>term~>name = lowerCase(rectpin~>pin~>term~>name) rectpin~>pin~>name = lowerCase(rectpin~>pin~>name) );foreach The problem is that manually changing the pin name and terminal name changes the connectivity net name. Doing this with a script doesnt. And changing the connectivity net name is not possible with a script and also not possible manually. Does anyone know a solution to this problem? Thanks in advance! Bert
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Forum Post: RE: Problem changing the net name of a pin through a script.
Hi Bert, When you say "connectivity" you mean the net name correct? Add this line into your foreach loop: rectpin~>pin~>term~>net~>name = lowerCase(rectpin~>pin~>term~>name) Changing a terminal name does not automatically change the name of the net this terminal is attached to. Max
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Forum Post: RE: Problem changing the net name of a pin through a script.
Hi Max, I get the error message: Cannot set attribute - name on that line. As far as I know this is linked to the terminal name and should be updated when the terminal name is updated. This is the case when you manually do it in the layout. Is there a way to an "apply after changing teh terminal name in a script? Thanks, Bert
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Forum Post: RE: Cadence Liberate Characterization Help
Sorry, but I though you were still asking about VSS related power in your last question. To debug any characterized values, you can use the following commands to save the Spice deck. After the run, go to the specified deck_dir and open the map.lst file to find the corresponding subdirectory for each arc. Open the sim.sp and remove the save=none option. re-run this deck. After simulation, use VIAV to view the waveform. If there are differences between these results and your schematic simulations, look into the sim.sp. If you see anything wrong, we will need to have a full test case to investigate. set_var extsim_deck_dir set_var extsim_save_passed deck
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Forum Post: How to simulate a fully differential input/output buffer .ibis model in Cadence Virtuoso?!
Hello, Could you please layout the details, how to simulate a fully differential output buffer(Tx) and fully differential input buffer(Rx) ibis model in Virtuoso?! The ibis buffer from analogLib is not working in differential mode. Beside there are no options to specify the io signal type (e.g. if the signal io is P/N type). Also I could not specify the Pin number! Only the Model name is not sufficient in my case. I wish to declare the pin number and type of signal along with the model name such that the io buffer could identify the target model distinctly within the XXX.ibs file. Kindly give your suggestion ASAP. Regards, Bitan Virtuoso Version: 6.1.6-64b Simulator: Specter
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Forum Post: How to simulate a fully differential input/output buffer .ibis model in Cadence Virtuoso?!
Hello, Could you please layout the details, how to simulate a fully differential output buffer(Tx) and fully differential input buffer(Rx) ibis model in Virtuoso?! The ibis buffer from analogLib is not working in differential mode. Beside there are no options to specify the io signal type (e.g. if the signal io is P/N type). Also I could not specify the Pin number! Only the Model name is not sufficient in my case. I wish to declare the pin number and type of signal along with the model name such that the io buffer could identify the target model distinctly within the XXX.ibs file. Kindly give your suggestion ASAP. Regards, Bitan Virtuoso Version: 6.1.6-64b Simulator: Specter
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Forum Post: Crefer data is not visible on schematic page
HI, I am using Allegro Concept HDL 16.6 version. I have created design having two pages and connected the pages using OFFPAGE connector( IN and OUT). I have given the same signal names as well. i am able to generate the Crefer without any error, but the Crefer data is not visible in the schematic pages near the ports as to which page the signal is going. Kindly help me on this issue. i have attached the screenshots for more information. Chadga.
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Forum Post: RE: how to find floating pins in layout
Hi LakshmanQual, Check this out. Hope this help. /* Purpose : Find floating pins in the layout by its connectivity. How to run : 1. load "/home/eda/SKILL_VXL/float_pins_check.il" 2. fc() Date created : June 2, 2018 Author : Marben F. Orallo */ ; load "/home/eda/SKILL_VXL/float_pins_check.il" procedure(fc() ; pin_name = "Ch1" cv = geGetEditCellView() pins = cv~>terminals~>pins pins_flatten = CCSflattenList(pins) pin_id = setof(x pins_flatten x~>name) incomplete_nets = lceGetIncompleteNets(cv)~>name foreach( pin_id pin_id netname = pin_id~>net~>name exist = member( netname incomplete_nets ) if( exist != nil then ; printf("\n exist me = %L", exist) loc = centerBox(pin_id~>fig~>bBox) printf("\n Connection found, connection is not yet finish. %L %L" pin_id~>name loc) ) ;if ) ;for ) ;proc procedure(CCSflattenList(l) if(listp(l) mapcan('CCSflattenList l) list(l)) )
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Forum Post: RE: Problem changing the net name of a pin through a script.
Hi Bert, Actually the terminal name doesn't have to be the same as the net name; changing the term name (which you can do by setting the name attribute on the terminal object) does not update the net name. You cannot directly change the net name; you have to create a new net with the lowerCase name (e.g. using dbMakeNet) and then use dbMergeNet to merge the original net into the new net. Hopefully that gives you enough clues? Regards, Andrew
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Forum Post: RE: Porting a design from one technology to another (even the finished layout)
Hi Matthew, I fixed the broken link to the COS article in that thread, but the article is actually all about schematic migration not layout migration. We do have a tool called Virtuoso Layout Migrate which is intended for this purpose, but it's normally only provided under a services engagement because the setup is quite complex and hard to set up; usually the benefit is when you have a lot of similar designs that need migrating as the effort needed to polish the migration can be significant. If you're interested, please contact your account team. Not sure it's necessarily what you're looking for though... Regards, Andrew.
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Forum Post: RE: How to simulate a fully differential input/output buffer .ibis model in Cadence Virtuoso?!
Please follow this up with customer support . I'm not that familiar with the ins and outs (excuse the pun) of IBIS; certainly in IC617 there seem to be a lot of choices for the ibis_buffer which change the symbol but I'm not sure whether it's what you want. Contacting customer support would allow us to redirect your query to somebody who knows about this in more detail. You might also want to check with a recent IC617 hotfix just in case (since IC616 is old and unsupported now). Regards, Andrew.
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Forum Post: RE: How to pass desVar using include file in ocean runs
Hi Prasad, When you say "both didn't work", what exactly didn't work? What was the error? Just trying to understand what you'd tried and what didn't work. The path() function specifies a list of directories to search in, and the definitionFile is the name of an actual file to include; relative paths are found using the directories specified in path(). Regards, Andrew.
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Forum Post: RE: Porting a design from one technology to another (even the finished layout)
Hi Andrew, Thanks for the reply. That's the information I was looking for. I had in mind that it was "significant effort" but just wanted to check. I'll see if the Layout Migrate is of interest. Best regards, Matt
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Forum Post: RE: Generating Gerber RS274X In 2:3 Format & Gerber File Syntax Issue.
Hi Paul, I am having the same trouble with resolution. I want RS274X 2.4. I tried changing the design parameter resolution to 0.1 mil (sounds logical - right?). However, the artwork form is not happy until the resolution is 5. Did you get this resolved? Thanks, Emmett
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Forum Post: RE: ade assembler output expression plot by matlab
thanks,Andrew, is there any doc or page for your useage of second getData, and if the output setup to expression, how to plot by matlab"?
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Forum Post: Need to perform boolean operation on layers
Hi , I want to access shapes in lower hierarchies in layout and do boolean operation to generate layer in current level. Is there any way I can have access to shapes in lower levels. (it helps in fixing softcheck during lvs verification easily.) Thanks, Raghu
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Forum Post: RE: ade assembler output expression plot by matlab
Well, 'help getData' gives a bit of a clue, but it's not that clear. I have an action to file some CCRs to get this improved to make it a bit more usable (on my to-do list). Not sure what you mean by the second half of your question? Andrew.
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Forum Post: RE: Need to perform boolean operation on layers
Hi Raghu, The abe (Advanced Boolean Engine) functions that were introduced in IC617/ICADV122 are what you want here. If you're going to use them though, please make sure you're using at least IC617/ICADV123 ISR9 or later; there were some issues in early versions which were fixed with an incompatible change to how they're used (the incompatible change happened sometime earlier than ISR9, but since ISR9 is when they started to be supported in PCells, that's a good "earliest version" to pick). BTW, the "abe" is nothing to do with my usual "ab" prefix - it's a coincidence that it looks like my name! Andrew.
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