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Forum Post: Error while trying to simulate simple VHDL testbench using ams simulator

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Hello, The setup is the same as described in my previous topic: block_A - VHDL stimule block_B - some VHDL combinatorial logic block_C - schematic where block_A and block_B are connected When I run this setup in ams, elaborator fails: ncelab: *E,MTOMDU: More than one unit matches 'library1.block_C:schematic': module library1.block_C:schematic (VST) architecture \library1\.block_C:schematic (VST) Any suggestions ? Thanks.

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