Hi all, Recently I am writing a simple verilog-A ADC and using variable-port width for the output bits. After I use "parameter integer nbit=7" in the verilog-A file and finish the verilog-A parsing, I can only see bit in the generated symbol. After reading [SOLVED] Verilog-(AMS) PCell with variable bus width Creating a component that allows setting a value on a bus in an analog simulation and this Parametrized busses in Verilog-A I start to build my symbol with SKILL. After loading the SKILL I can observe the port now can change with nbit parameter. But again, during spectre netlisting it throws out an error saying the verilog-A view is not synchronised with the symbol. After updating the symbol from verilog-A, the variable-port width again becomes bit only. I think this issue must have been reported and discussed before. But can anyone provide some references to it? Thanks in advance. PS: Attached are my verilog-A and SKILL code. PPS: Now I am using Virtuoso 6.1.6 community.cadence.com/.../VerilogA.txt community.cadence.com/.../SKILL.txt
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