Forum Post: RE: Problem with Liberate and Verilog-A Model
Please try the following, In your sim.sp, add .hdl . Then run sim.sp, using spectre +spice +aps sim.sp . Check sim.log. If no errors, then, modify extsim_deck_header as below, set_var...
View ArticleForum Post: RE: Converting .MAX file to .BRD File issue
got it to work, ran orcad as administrator and copied the whole folder to C:\ then ran db doctor.
View ArticleForum Post: Synthesizing Specific Gates in Cadence Genus
Hello Cadence Community, I'm working on a flattened netlist in Cadence Genus for a design and would like to apply targeted synthesis optimizations to a specific list of gates (e.g., g1234, g5678) while...
View ArticleForum Post: Start Analysis button does nothing
Im very new to Cadence EDA. Im trying to SI analysis but after I choose the nets to analyze and go to click "Start Analysis" it does nothing. I have installed the program in a place other than the C...
View ArticleForum Post: Part List Filter Won’t Clear in OrCAD 17.4 – Any Fix?
I'm currently using OrCAD Capture version 17.4-2019 S019, and I'm having trouble clearing the part list filter — it simply won’t reset. I noticed two other posts reporting the same issue, but neither...
View ArticleForum Post: Updating Wire Alias Name as Schematic and Flat Netname
HI, Im trying to update wire alias name as schematic and flat netname i tired in two different ways, but it remains the same. Can anyone please help me to find the solution. Program: SetOptionBool...
View ArticleForum Post: RE: Synthesizing Specific Gates in Cadence Genus
# Mark all cells dont_touch set_dont_touch [get_cells *] # Clear dont_touch on target gates only foreach gate {g1234 g5678} { set_dont_touch -clear [get_cells $gate] } # Optionally set mapping...
View ArticleForum Post: RE: Part List Filter Won’t Clear in OrCAD 17.4 – Any Fix?
Just put the * character in the edit box and press the enter key.
View ArticleForum Post: RE: Start Analysis button does nothing
Check the PCB Editor Command Prompt for any messages. You need the SIGRITY_EDA_DIR Windows Environment Variable set to allow PCB Editor to find the Sigrity installation and you need to use the correct...
View ArticleForum Post: Place Replicate?? Moving circuits from top layer to bottom layer.
So I tried in Presto to move a bunch of components with tracks and then shove them to the bottom layer and it makes a huge mess. In Altium, I could just grab stuff, flip it to the other side and it's...
View ArticleForum Post: RE: Place Replicate?? Moving circuits from top layer to bottom...
I tried putting up a link to the training video showing how to place replicate, but not showing how to undo it, but it's getting flagged.
View ArticleForum Post: RE: I want to generate the Pin Pair for the netclass using one net
You want to achieve all of this using SKILL? or just in general any method?
View ArticleForum Post: RE: Start Analysis button does nothing
Hello, if I search for Sigrity Aurora in Start, go to the location, copy the path (C:\Cadence\SPB_23.1\tools\bin) and add it the system variables it now gives me this error when I press "Start...
View ArticleForum Post: RE: Synthesizing Specific Gates in Cadence Genus
Thanks for your reply. I faced couple of questions. First, the "-clear" was not a valid option for me an I needed to use the following command, and I wanted to ensure it's still correct: #...
View ArticleForum Post: RE: I want to generate the Pin Pair for the netclass using one net
Hi Elecguy, Not using SKILL, in general method
View ArticleForum Post: RE: Updating Wire Alias Name as Schematic and Flat Netname
Hi kartikey, While you’re iterating over the properties of the schematic net, I noticed that you’re trying to update the “Net Name” property. Instead, you should be updating the “Name” property of the...
View ArticleForum Post: RE: Start Analysis button does nothing
You need an installation of the Sigrity products to support the Workflows within PCB Editor. SPB 23.1 Base needs Sigrity 2023.1 HF2, SPB 23.1 QIR1, and later, needs Sigrity 2023.1 HF3 to Sigrity 2024.0...
View ArticleForum Post: RE: Updating Wire Alias Name as Schematic and Flat Netname
HI, Thanks for the reply... Still remains the same not updated.
View ArticleForum Post: RE: How to properly move a part between OLBs with TCL?
andakConsultingLtd Please below api instead of DeletePackage: RemovePackage(pPackage) : returns DboState Class : DboLib(DboBaseObject): Parameters: pPackage: DboPackage * $lDboLibrary DeletePackage...
View ArticleForum Post: RE: Problem with Liberate and Verilog-A Model
Adding .hdl solved the error. Thank you!
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