From the code it seems that vref is reference node for output voltage. However, when I run the test Vout doesn't change when vref change over all range. So what is the function of it? This is the nest list: // Generated for: spectre // Generated on: Jun 16 16:55:17 2018 // Design library name: TEST // Design cell name: Test_opamp // Design view name: schematic simulator lang=spectre global 0 // Library name: TEST // Cell name: Test_opamp // View name: schematic I0 (Vout VREF Vin net03 AVDD AVSS) opamp gain=1M freq_unitygain=30M rin=1T \ vin_offset=0 ibias=0 iin_max=100u rout=10 vsoft=0.5 slew_rate=1M V5 (net07 0) vsource dc=1 type=dc VREF1 (VREF 0) vsource dc=0 type=dc AVSS1 (AVSS 0) vsource dc=0 type=dc AVDD1 (AVDD 0) vsource dc=5 type=dc Vin1 (Vin net07) vsource mag=1 phase=0 type=sine ampl=100.0m sinephase=0 \ freq=1K R1 (net03 Vout) resistor r=9K R0 (net07 net03) resistor r=1K simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ checklimitdest=psf tran tran stop=10m write="spectre.ic" writefinal="spectre.fc" \ annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile saveOptions options save=allpub ahdl_include "/home3/tool/IC616/tools/dfII/samples/artist/ahdlLib/opamp/veriloga/veriloga.va"
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