Virtuoso does not support parameterised bus pins and hence this makes doing this slightly trickier. The good news is that it's not impossible - you need to create PCells for the symbol and also the netlist.oa view within the veriloga view, and a netlist procedure so that spectre knows how to netlist the variable connectivity. I've been meaning to put together an example of how to do this for some time, so this gave me the excuse! Please find the code below (see the comments within). Note that you will need to change the VerilogA code slightly - it should be: input [0: bits-1 ] in; voltage out, clk; voltage [0: bits-1 ] in; Regards, Andrew. /* abGenericDAC.il Author A.D.Beckett Group Custom IC (UK), Cadence Design Systems Ltd. Language SKILL Date Jul 25, 2018 Modified By SKILL code to support a veriloga model with a variable width bus as input - in this case a DAC model. Works by creating PCells and a netlist procedure to handle the varying connectivity. First create a veriloga view with this content, and then call abCreateGenericDACViews() (with appropriate arguments) to create the symbol pcell, the pcell for the netlist.oa, and the CDF. Note that the pins need to match between the veriloga and the pcell code (and netlist procedure), and the parameters need to match the CDF in the creation code below. This file will also need to be loaded from the libInit.il within the library containing the component so that the netlist procedure is loaded when the library is first accessed in each session. `include "constants.vams" `include "disciplines.vams" module genericDAC(out, in, clk); parameter integer bits = 4; parameter real fullscale = 1.8; parameter real td = 0; parameter real tt = 0; parameter real vdd = 1.8; parameter real thresh = 0.9; output out; input clk; input [0:bits-1] in; voltage out, clk; voltage [0:bits-1] in; real aout; integer weight; genvar i; analog begin @(cross(V(clk) - thresh, 1) or initial_step) begin aout = 0; weight = 2; for(i = bits - 1; i>=0; i = i-1) begin if(V(in[i]) > thresh) begin aout = aout + fullscale/weight; end weight = weight*2; end end V(out) " bits-1)) netClk= dbMakeNet (cv "clk" ) netOut= dbMakeNet (cv "out" ) ;---------------------------------------------------------------- ; create the terminals ;---------------------------------------------------------------- dbCreateTerm (netIn netIn~>name "input" ) dbCreateTerm (netClk netClk~>name "input" ) dbCreateTerm (netOut netOut~>name "output" ) ;---------------------------------------------------------------- ; create the pins ;---------------------------------------------------------------- dbCreatePin (netIn figIn) dbCreatePin (netClk figClk) dbCreatePin (netOut figOut) ;---------------------------------------------------------------- ; Put some labels for the pins ;---------------------------------------------------------------- dbCreateLabel (cv list ( "pin" "drawing" ) pl+ps/2:0 netIn~>name "centerLeft" "R0" "stick" lh) dbCreateLabel (cv list ( "pin" "drawing" ) pl+ps/2:-ps netClk~>name "centerLeft" "R0" "stick" lh) dbCreateLabel (cv list ( "pin" "drawing" ) bw+pl-ps/2:0 netOut~>name "centerRight" "R0" "stick" lh) ;---------------------------------------------------------------- ; And other symbol labels ;---------------------------------------------------------------- label= dbCreateLabel (cv list ( "annotate" "drawing7" ) bw+pl-ps/2:ps*1.5 "cdsName()" "centerRight" "R0" "stick" lh) label~>labelType= "ILLabel" label= dbCreateLabel (cv list ( "annotate" "drawing" ) pxc:0 "cdsParam(1)" "centerLeft" "R0" "stick" lh) label~>labelType= "ILLabel" label= dbCreateLabel (cv list ( "annotate" "drawing" ) pxc:-ps "cdsParam(2)" "centerLeft" "R0" "stick" lh) label~>labelType= "ILLabel" dbSetConnCurrent (cv) t ) ; let )) dbSave (pcellId) dbClose (pcellId) ;-------------------------------------------------------------------- ; Create the pcell in the "shadow" database (netlist.oa) in the ; veriloga view. This is so the terminals match in the switch view. ; Can't use pcDefinePCell because that creates a "master" OA ; database, and this needs to be done as a non-master database (the ; master is the veriloga.va file). So this works by creating a file ; with the code in, and then using dbDefineProc to associate it with ; the cellView (see further down). ;-------------------------------------------------------------------- tempFile= makeTempFileName ( "/tmp/pccode" ) tempPort= outfile (tempFile) pprint ( ' procedure (pcGenCell(cv "d" ) let ((pcParams bits) pcParams=cv~>parameters bits=pcParams~>bits unless ( fixp (bits) bits=4) let ((netIn netClk netOut) netIn= dbMakeNet (cv sprintf ( nil "in " bits-1)) netClk= dbMakeNet (cv "clk" ) netOut= dbMakeNet (cv "out" ) dbCreateTerm (netIn netIn~>name "input" ) dbCreateTerm (netClk netClk~>name "input" ) dbCreateTerm (netOut netOut~>name "output" ) ;---------------------------------------------------- ; this is to stop the instance being omitted ; because there's no hierarchy ;---------------------------------------------------- dbCreateProp (cv "nlAction" "string" "stop" ) dbSetConnCurrent (cv) ) )) tempPort ) newline (tempPort) close (tempPort) ;-------------------------------------------------------------------- ; Now create the non-master database (that's what the "wc" is for). ; Has to create the parameters hier prop and the pcell parameter ;-------------------------------------------------------------------- pcellId= dbOpenCellViewByType (library cell "veriloga" "netlist" "wc" ) params = dbCreateHierProp (pcellId "parameters" ) dbCreateProp (params "bits" "int" 4) dbDefineProc (pcellId tempFile) dbSave (pcellId) dbClose (pcellId) deleteFile (tempFile) ;------------------------------------------------------------------------ ; Now create the CDF ;------------------------------------------------------------------------ let ( ( cellId cdfId ) unless ( cellId = ddGetObj ( library cell ) error ( "Could not get cell %s." cell ) ) when ( cdfId = cdfGetBaseCellCDF ( cellId ) cdfDeleteCDF ( cdfId ) ) cdfId = cdfCreateBaseCellCDF ( cellId ) ;;; Parameters cdfCreateParam ( cdfId ?name "bits" ?prompt "bits" ?defValue 4 ? type "int" ?display "t" ) cdfCreateParam ( cdfId ?name "fullscale" ?prompt "fullscale" ?defValue "1.8" ? type "string" ?display "t" ?parseAsNumber "yes" ?parseAsCEL "yes" ) cdfCreateParam ( cdfId ?name "td" ?prompt "td" ?defValue "0" ? type "string" ?display "t" ?parseAsNumber "yes" ?parseAsCEL "yes" ) cdfCreateParam ( cdfId ?name "tt" ?prompt "tt" ?defValue "0" ? type "string" ?display "t" ?parseAsNumber "yes" ?parseAsCEL "yes" ) cdfCreateParam ( cdfId ?name "vdd" ?prompt "vdd" ?defValue "1.8" ? type "string" ?display "t" ?parseAsNumber "yes" ?parseAsCEL "yes" ) cdfCreateParam ( cdfId ?name "thresh" ?prompt "thresh" ?defValue "0.9" ? type "string" ?display "t" ?parseAsNumber "yes" ?parseAsCEL "yes" ) ;;; Properties cdfId->formInitProc = "" cdfId->doneProc = "" cdfId->buttonFieldWidth = 340 cdfId->fieldHeight = 35 cdfId->fieldWidth = 350 cdfId->promptWidth = 175 ;-------------------------------------------------------------------- ; note that this needs a netlist proc so that it can ; handle the variable number of pins ;-------------------------------------------------------------------- cdfId->viewInfo = '( nil veriloga ( nil moduleName "genericDAC" namePrefix "ahdl" netlistProc abGenericDACNetlistProc stringParameterList nil parameterList (bits fullscale td tt vdd thresh)) ) cdfSaveCDF ( cdfId ) ) ) ; let ) /**************************************************************** * * * abGenericDACNetlistProc(inst) * * * * Netlist procedure to netlist the instance. Mostly standard * * other than the list of terminals which is constructuted based * * on the bits parameter. * * * ****************************************************************/ procedure (abGenericDACNetlistProc(inst) let ((formatter netlister termList bits) formatter=nlGetFormatter(inst) netlister=nlGetNetlister(formatter) nlPrintInstComments(formatter inst) nlPrintIndentString(netlister) nlPrintInstName(formatter inst) ;---------------------------------------------------------------- ; Output the correct terminal list ;---------------------------------------------------------------- bits=atoi(nlGetParamStringValue(inst "bits" )) nlPrintString(netlister " ( " ) termList=`( "out" ,@ dbProduceMemName ( sprintf ( nil "in " bits-1)) "clk" ) foreach (term termList nlPrintString(netlister nlGetTerminalSignalName(inst term) " " ) ) nlPrintString(netlister ") " ) nlPrintModelName(formatter inst) nlPrintInstParameters(formatter inst) t ) )
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