Hi Ganesh, You'll only have connectivity in the layout if it was generated with VLS XL (probably). Even then, the layout database does not get marked that the connectivity is up to date so that the design can be netlisted. However, even if I do that (which could be done using SKILL), you may also have problems if there are pins on the devices which do not have connectivity - for example the bulk pins on transistors which are connected to the substrate - often the substrate is not "connected" in VLS XL, and hence you'd have an incomplete netlist. So there's a lot of reasons why this would be hard to do. Even then, what are you comparing? Virtuoso Layout Suite XL is going to check against the schematic for what it knows about - so running LVS on a netlist produced from the layout connectivity database is not going to tell you much that VLS XL didn't already tell you. The point of a physical verification tool is to have a "signoff" tool that will extract the devices from the shapes in the layout and extract the connectivity and then compare that. So I don't think what you're asking for is really feasible (at least not unless there are a lot of joined up conditions), and even if you can make it work in practice I'm not sure it's going to be terribly useful as an alternative to doing a proper LVS. Regards, Andrew.
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