This is a challenge, because the mapping performed to convert between spectre syntax and Verilog syntax for the bus gets in the way. There was an earlier discussion that I was party to in CCR 1544227 and I don't think there was really a way then - although there was sort-of a suggestion that I0.Vint\ would work (from my experiments though, it doesn't). I was using IC617 ISR23 (so slightly newer than you) and an XCELIUM release, but I think it's a limitation of deepprobe (I created deepprobe in the first place, so blame me...) The workaround I suggested in the earlier CCR was to place an instance of patch in the lower level cell to alias the Vint net to something which wasn't a bus (e.g. Vint_bit_2) and then you can deepprobe to that instead. Not ideal, but better than nothing. You probably should contact customer support to see whether we can do anything to fix this properly (especially now that deepprobe is in analogLib rather than being AE-ware). Thanks Andrew
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