Hi Steve, Thanks for your response. Perhaps I was unclear, the problem occurs after editing the code, not at compilation -- there I can include the 'defines.v' file and everything works fine (of course, during the sim, not having missing symbols is pretty important..). What I would like is a way to include the same 'define.v' with the process that extracts the Verilog from the text editor, i.e. when teSaveAndExtract() runs. So far, I've edited the hdl.var with some '-define AA=0' statements, but as you say, this is brute force and not scalable. My best bet was to use the -INCDIR statement in the same hdl.var, but that doesn't seem to work, or I'm not configuring it properly. Do you have any other ideas? Thanks! Caspar
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