These are non UVM based testbenches. These are self checking verilog based testbenches. At the end of the test a log message is dumped out with pass/fail information or number of simulation mismatches. But during the run, lot of log messages are generated which unnecessarily increases the disk space. For a preliminary regression it is enough if I get the information of pass/fail. If the testcase fails then I will be using waveform based debug option. What do you mean by debug mode?
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