It looks like you are using a legacy workflow with Incisive, where you defined a cds.lib and hdl.var file, and invoked the ncvlog, ncelab and ncsim directly. The error message comes because the compiled design refers to a Verilog (or VHDL) library name that wasn't listed in your cds.lib file. I would guess that you used a valid cds.lib when compiling the design but that you're simulating in a different directory where you either have no cds.lib, or the wrong cds.lib.
↧