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Forum Post: RE: Cadence layout suite XL - some overlap regions get highlighted in yellow

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Hi, what is the message in the Annotaion Browser? Also select one of the instances and check the pin connectivity in the Property Editor Assistant. I can give you only pointers here. Without knowing the pdk and design it pretty hard to tell exactly whats going wrong. A LVS clean design is not necessarily XL clean. You can manually draw a transistor with a bunch of polygons and your LVS might be happy about it, while XL is not able to identify any device out of this stack of shapes. Regards, Marc

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