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Forum Post: RE: AMS simulation error after removing a verilogA cell from the testbench

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I've not found any records of that error reporting issues with generated_skeleton_ahdl messages. I think this would be much easier to debug via customer support , as otherwise there would need to be quite a bit of guess work. Is this module instantiated in a hierarchical VerilogA module? Which INCISIVE subversion are you using (what does "irun -version" give in the terminal window)? Are you using UNL (Unified Netlister) on the Simulation->Netlist and Run options form? Have you tried checking the "Clean snapshot and pad files" on that form? Regards, Andrew.

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