Dear Giuseppe and Andrew, I was just about to post the original reference only to see that Giuseppe already did! That reference is exactly the paper I read some time ago. If it helps at all, there is a recent paper (2017) entitled “Analysis and validation of low-frequency noise reduction in MOSFET circuits using variable duty cycle switched biasing” that compares the 1/f noise of a conventional stationary Cadence IC-615 spectre pss/pnoise analysis of a multistage ring VCO with simulation results of the author’s proposed model that includes the impact of the switched 1/f noise (Figure 7). This paper, cited below, might be if interest to either of you or your R&D personnel. Shawn Jainwal, M. Sarkar and K. Shah, "Analysis and Validation of Low-Frequency Noise Reduction in MOSFET Circuits Using Variable Duty Cycle Switched Biasing," in IEEE Journal of the Electron Devices Society, vol. 6, pp. 420-431, 2018. doi: 10.1109/JEDS.2018.2802899 ieeexplore.ieee.org/.../8290662
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