File->Import->SPICE can also read spectre netlists. If you really must do it in SKILL, you'd want to use either the db functions (dbCreateInst, dbCreateNet/dbCreateTerm/dbCreatePin) or more simply use the sch functions schCreateInst/schCreatePin/schCreateWire. I have tended to use schCreateWire/schCreatePin but still use dbCreateInst (schCreateInst doesn't add much value). If it's a transistor level circuit, you'll also have to set the properties on the devices themselves using either dbCreateParamInst or similar, or using dbReplaceProp or instId~>w="2u" etc, and may then want to call the CDF callbacks (search in these forums for abInvokeCdfCallbacks or on support.cadence.com for CCSinvokeCdfCallbacks). Here's some code which generates a big schematic that I used for testing something. Might give you a clue, although I didn't add many comments, and it's in Lisp syntax, which you may not be familiar with: /* abCreateBigSchematic.il Author A.D.Beckett Group Custom IC (UK), Cadence Design Systems Ltd. Language SKILL Date Jul 25, 2014 Modified By Silly example to create a big schematic in order to exercise the performance of some of the tools. Note that this makes a number of wild assumptions - for example, that there will be only 2 pins on each cell being arrayed. *************************************************** SCCS Info: @(#) abCreateBigSchematic.il 07/25/14.12:45:52 1.1 */ ( defun abCreateBigSchematic ( @key (cv ( geGetEditCellView )) (numInsts 1000) (numParallel 10) (lib "analogLib" ) (cell "res" ) (view "symbol" ) (stepX 0.5) (stepY 1.0) (stubLength 0.125) (textHeight 0.0625) verbose) ( let (master (x 0) (y 0) pinLocations pinMaster netName1 netName2 wire numRows) ( setq master ( dbOpenCellViewByType lib cell view)) ( setq pinMaster ( dbOpenCellViewByType "basic" "iopin" "symbol" )) ( setq pinLocations ( foreach mapcar terminal ( dbGetq master terminals) (centerBox ( dbGetq ( dbGetq ( car ( dbGetq terminal pins)) fig) bBox)) )) ( schCreatePin cv pinMaster "PLUS" "inputOutput" nil ( list x y) "R0" ) ( setq netName1 "PLUS" ) ( setq y ( plus y stepY)) ( setq numRows ( quotient numInsts numParallel)) ( for row 1 numRows ( when ( and verbose ( zerop ( mod row 100))) ( printf "Row %d\n" row)) ( if ( equal row numRows) ( setq netName2 "MINUS" ) ( sprintf netName2 "net_%d" row)) ( setq x 0) ( for col 1 numParallel ( dbCreateInst cv master "" ( list x y) "R0" ) ( foreach (pinLoc netName) pinLocations ( list netName1 netName2) ( setq pinLoc ( dbTransformPoint pinLoc ( list ( list x y) "R0" 1))) ( setq wire ( schCreateWire cv "route" "full" ( list pinLoc ( list ( plus (xCoord pinLoc) stubLength) (yCoord pinLoc))) 0.0625 0.0625 0)) ( schCreateWireLabel cv ( car wire) pinLoc netName "lowerLeft" "R0" "stick" textHeight nil ) ) ( setq x ( plus x stepX)) ) ( setq y ( plus y stepY)) ( setq netName1 netName2) ) ( schCreatePin cv pinMaster "MINUS" "inputOutput" nil ( list x y) "R0" ) ( schCheck cv) ( dbSave cv) t ) ) Regards, Andrew.
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