Thanks Tawna and Andrew for the replies. I was mostly after generic advice/best practices/things_to_avoid for analog designs up to 10GHz if anyone has experience of routing/bonding/grounding in the top metal layers. It is not for anything specific. The foundry only states rules on how to avoid getting DRC errors. I realise this is more planning/design related rather than layout tool related so might be outside the scope of this forum (in which case no worries). Some requested details below: Analog Routing/Grounding Layout XL in Cadence Virtuoso IC617 BiCmos Process Thanks.
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