Hi, while doing AMS simulations like SystemVerilog (with EEnet package) in Virtuoso I am stuck with a rise-time limit for my output signals. The IEs (interface elements) that are automatically put in between analog signals (spectre) and the SystemVerilog domain do have different parameters to adjust the electrical behaviour. Among these parameters there is "Ts" which defines the sample rate for the interface signal conversion. The default value is 1ns, but my circuit operates with 800ps pulses and requires a rise-time of <100ps. I was able to reduce to Ts=500ps and the egdes became faster, but when reducing Ts further the simulation will get stuck and not finish. I do have the feeling that the "Ts" parameter requires some relation to other time parameters of the IEs or the AMS simulator, but I do now know which ones. Does anyone know how to setup the IEs and AMS simulation for fast signals with risetimes <100ps ?
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