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Forum Post: RE: verilogA simulation of 2nd order Sigma-Delta modulator

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First of all, this is a community forum - it's not an "ask Andrew" forum. I do this in my spare time (it's not part of my job) - I squeeze responses in when I can. I'm not going to sit and re-enter the schematic and guess what you've chosen on the model writer settings to produce each model - I simply don't have the time. Maybe somebody else would be more generous, but I suggest you contact customer support with a complete testcase . The chances are you've accidentally created a positive feedback loop, but without seeing the actual data it would be hard to determine that. Regards, Andrew.

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