This is with 95% a question without solution but I still try it .. maybe there is something out there. For noise the different sources are visible in the results browser and noise summary so I can identify the devices/sources which kill noise performance. I would be looking for something similar for linearity (e.g. IIP3, HD3, IM3, ...). The issue: A simple differential pair (PMOS with NMOS loads or reverse). The IIP3 versus VGS, VDS, GM/ID etc looks arbitrary and I have no control what is limiting linearity. I can get a relatively accurate expression for IIP3 for drain current linearity but this is 30-40 dB (!!) better than what I get. So I assume I am limited by ids/vds linearity. But is it the gm transistor or the load? And what know to dial to get a handle on this? Some sort of "nonlinearity" separation could confirm that I may neglect the common ids/vgs nonlinearity and just plot IIP3 vs. VDS of a single transistor.
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