This went into moderation because the repeated text triggered the automated spam detection. Once you'd confirmed it was genuine, it came to me as a moderator to approve, which I then did - clearly it's not spam, but repeated text is a common signature of spam (and believe me, I've had to deal with quite a few genuine spam attacks over the years) - my apologies for it being held up. Anyway, the issue with hierarchy within generate blocks (or genvar in this case) is that the hierarchy editor and netlister traversal needs to have a representation to allow it to work out what the underlying block is to be netlisted. Given that depending on the parameter value that affects the expansion, there may be memoire_bit present (or not), it can't produce a representation in the database which captures that - strictly it's not known until run-time (when the simulator elaborates the design) what is within the block, and that variable content cannot be stored within OpenAccess representation. This is a known limitation that is (I believe) documented. The workaround is to reference the Verilog-AMS representation of memoire_bit as an external file via the Simulation->Options menu in ADE. The fact that it doesn't show up in the hierarchy editor doesn't matter, because you're just telling the simulator to include the lower level directly (yes, I know it's a pain, but luckily this happens fairly rarely). Regards, Andrew.
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