The current issue where I found myself clueless, is I am having connectivity problems. Though I checked the connectivity manually, but it doesn't resolve the problem in layout. There are two distinct connectivity problems. 1. The bulk is shorted with the source in case of PMOS. However in layout, it is not recognised. The layout still recognises them differently. The circuit has a low voltage part and a high voltage part. For the low voltage MOS I have VDD and VDDS. Whereas, for the high voltage part there is VDD1. VDD and VDD1 are connected to the corresponding PMOS and VDDS is connected to the bulk of low voltage PMOS. However, PMOS in the higher voltage side in the layout is searching for vdds. 2. In layoutXL, one can check the connectivity in the layout corresponding to the schematics if a schematic driven layout is drawn. Since I drew the layout completely manually, even if I try to open it in LayoutXl; it doesn't help me to check the connectivity. Perhaps it would be nicer to have something like that.
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