HI In our design, I see some weird behavior on the waveform. The logic is simplified as following always_ff @(posedge clk) begin A <= B; end It is supposed to be a flop. However, the A changes at the same clock edge as B. I am expecting there are some racing between clk and B in simulator but not sure what happens. How do I debug this ? We are using xcelium and simvision. Appreciate any help. Chris
↧