[quote userid="178062" url="~/cadence_technology_forums/f/custom-ic-design/48008/generating-lib-file-for-synthesis-using-genus-from-transistor-level-cells-using-virtuoso/1375555"]if you have not defined power templates or skipped power characterization, this is certainly wrong.[/quote] I have defined all power, delay, and constraint templates. But the index values (that I calculated might be wrong). I calculated the the 3 values for index_1 as the "(riseTime + fallTime) / 2" for 1, 4 and 20 inverter loads. they turned out to be 61.75 ns, 158.9 ns, 794.1 ns respectively. I calculated the index_2 values as input capacitances for 1, 4, and 16 inverter loads. 18.732 pF, 37.464 pF, 74.928 pF respectively. These are exactly what I used as index_1 and index_2. hence, index_1 = { 61.75 158.9 794.1 } and index_2 = { 18.732 37.464 74.928 } I have used these values for all three (delay, power, constraint) templates. [quote userid="178062" url="~/cadence_technology_forums/f/custom-ic-design/48008/generating-lib-file-for-synthesis-using-genus-from-transistor-level-cells-using-virtuoso/1375555"]In terms of long timing and index table, as I have suggested, you can define_min/max_transion and min_output_cap variables (check pdf doc). you simple define the size of index 1/2, eg , you need to define size. one of the install/example has such a template. then, use char_library -auto_index. the tool will create all slew/load table for you to satisfy you defined max_transition.[/quote] I did not understand this, can you please explain this a little more? I already did these as you'd suggested them earlier. I have already done this in template.tcl : set_var min_transition 6e-12 set_var max_transition 1e-06 set_var min_output_cap 1e-16 Am I supposed to remove the power delay and constraint templates when I use -auto_index in char_library? If required, am I allowed to request you for a short call? Thanks
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