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Forum Post: SKILL for Substrate Integrated Waveguide layout

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Folks, I've been looking for some generic custom SKILL (using virtuoso, IC6.1.7) to generate arrays of vias based on PDK-defiend minimum via spacing in a variety of different areas (polygons) between arbitrary metal layers, to include metal slotting for large connected areas. I'm building a number of 3D structures, include SIWs, in the BEOL and hand-generating these arrays for each structure is quite time consuming. Any pointers on where I should be looking? Regards, Jack

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