Hi we have many analoglib resistors in our schematic, we will be filtering these resistors and short the two terminals while running LVS by using (asura/pvs) commands, because these does not represent any physical device. but problem with this resistor is, it is breaking the connectivity in layout, Take an example of analoglib resistor "R", two terminals are connected to "netA" and "netB" respectively in schematic, while doing layout i suppose to ignore resistor(R) and short netA and netB. is there any way to update the layout connectivity by this way. we are able to filter out analoglib resistor connected nets by using below code, procedure(FilterAnalogLibResNets() cv = geGetEditCellView() analoglibres = setof(resinst cv~>instances resinst~>libName == "analogLib" && resinst~>cellName == "res") foreach(analoglibres1 analoglibres neta = car(analoglibres1~>instTerms)~>net~>name netb = cadr(analoglibres1~>instTerms)~>net~>name printf("Two terminals of Analoglib resistor are connected to net %s and net %s these two should short in layout \n" neta,netb) );foreach ) is there any way to update the layout connectivity by shorting neta and netb? Regards Naresh
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