The behavior does change if you move the declaration of the index 'i' into the for loop itself. That is because a local variable declared in a for loop creates its own SystemVerilog scope. module my_tb; initial begin : my_initial_block for (int i=0;i<1;i++) begin : my_for_block $display("%m"); end : my_for_block end : my_initial_block endmodule This has the output: my_tb.my_initial_block.unmblk1.my_for_block But you can label the for-loop itself. This is probably what you want to do. module my_tb; initial begin : my_initial_block for_loop: for (int i=0;i<1;i++) begin : my_for_block $display("%m"); end : my_for_block end : my_initial_block endmodule This has the output: my_tb.my_initial_block.for_loop.my_for_block
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