Hi Andrew, you are right it is router. Sorry, initially I sent you only behavioral code which is not required. Following is the synthesized code. In this code, there is no specification of power supplies anywhere. As I mentioned previously that default power and ground nets of standard cells are vdd! and gnd!. module decoder(i_en, i_data, o_data); input i_en; input [7:0] i_data; output [255:0] o_data; wire i_en; wire [7:0] i_data; wire [255:0] o_data; wire n_0, n_3, n_5, n_6, n_7, n_8, n_9, n_10; wire n_12, n_13, n_14, n_15, n_16, n_44, n_70, n_99; wire n_102, n_112, n_113, n_116, n_119, n_126, n_128, n_130; wire n_160, n_162, n_166, n_174, n_177, n_180, n_194, n_200; wire n_205, n_210, n_217, n_223, n_226, n_231, n_235, n_238; wire n_240, n_257, n_259, n_261, n_263, n_269, n_272, n_274; wire n_277, n_289, n_294, n_296, n_298, n_300, n_302, n_304; wire n_310, n_312, n_314, n_316, n_319, n_337, n_344, n_351; wire n_358, n_365, n_372, n_379, n_386, n_488, n_493, n_498; wire n_503, n_508, n_513, n_518, n_523, n_524, n_525, n_526; AND2_X6 g5993__8780(.A1 (n_316), .A2 (n_277), .Q (o_data[153])); AND2_X6 g5865__4296(.A1 (n_319), .A2 (n_314), .Q (o_data[190])); AND2_X6 g5867__3772(.A1 (n_319), .A2 (n_312), .Q (o_data[189])); AND2_X6 g5933__1474(.A1 (n_319), .A2 (n_310), .Q (o_data[188])); AND2_X6 g5854__4547(.A1 (n_316), .A2 (n_296), .Q (o_data[187])); AND2_X6 g5908__9682(.A1 (n_316), .A2 (n_314), .Q (o_data[186])); AND2_X6 g5915__2683(.A1 (n_316), .A2 (n_312), .Q (o_data[185]));
↧