Dear Andrew, Thank you again for reading my comments and adding your insight! Please allow me two comments. [quote userid="4936" url="~/cadence_technology_forums/f/custom-ic-design/56658/veriloga-module-in-a-crystal-oscillator-simulation-testbench-negatively-affects-simulation-parameters-for-oscillation/1388094#1388094"]For a start, the gear2only and traponly are slight misnomers - I always thought they should be called gear2mostly and trapmostly (!), because at breakpoints (such as the start/end of a transition in a voltage source or Verilog-A transition) it will always switch to euler for that time step[/quote] I understand this from the Cadence documentation. My understanding, rightly or wrongly, is that the choice of the "gear2only" algorithm will utilize gear2 as the dominant algorithm and to a greater extent than specifying "gear2". I am also well aware of the numerical damping the algorithm provides. However, this is easily overcome by a sustaining amplifier and its resonator with a reasonably robust design. In fact, if the algorithm is responsible for damping out an oscillation, it is probably a very good clue the design is not sufficiently robust! With respect to David's problem, I would think it would help the convergence as the integration seems to be overly sensitive to clock transitions. My personal experience, and I will only speak for myself, is that "gear2only" has provided the most robust convergence simulation results. [quote userid="4936" url="~/cadence_technology_forums/f/custom-ic-design/56658/veriloga-module-in-a-crystal-oscillator-simulation-testbench-negatively-affects-simulation-parameters-for-oscillation/1388094#1388094"] This is unlikely to help either, for two reasons: The output of the voltage source is still in the matrix and needs to be solved for, and so the sharp transition is still present [/quote] Having written a numerical integration algorithm many years ago, it seems to me the difficulty in a numerical algorithm converging on an ideal source with a discontinuity driving a series resistor [1] and it driving an arbitrary load impedance is significant. I have not experienced any integration issues when an ideal source drives a purely resistive load whose resistance value is reasonable. This was the motivation for my suggestion to David. If the Cadence algorithm reverts to a first-order integration algorithm in this case, I am surprised, but will accept your answer ! Shawn [1] i.e., a state voltage is not involved
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