Thanks for the detailed answer and the link. 2) After a discussion with our partner, it should work when I define the nettypes in my SV code (e.g. input wrealsum myinput; ) and include "import cds_rnm_pkg::*; ). The only thing the partner need to do is to replace "cds_rnm_pkg::*" with his tool-vendors predefined package (which uses the same predefined nettypes) and run the code. To keep the code flexible among different tools, a condition might be included to either import the "cds_rnm_pkg" ot the other tool-vendors package. This is something we need to try now. 1.1) To include the required packages (dmsLib, etc.) I am using the "CIW-->Tools-->AMS-->HDL Package Setup" feature, since it allows to configure the HDL setup not only for simulations, but also for compilation (Check&Save) from within the text-editor. Is this the tool you are referring to ? 1.2) I think Virtuoso 6.1.8 already uses AMS-UNL per default (at least it is the only option shown in the netlister settings) since I start it from a maestro-view. But regarding explicit, implicit or interconnect netlisting, I have no idea and a quick search on google and Cadence help did not help much. Do you have a link or can you give a brief explanation on the differences ? What I am doing right now is to define the ports of a module like this: import cds_rnm_pkg::*; module mymodule( input wrealmax myinput; output wrealsum myoutput; ) And I need to ensure that the ports of the connected modules do have the same nettype defined. Is this explicit netlisting ?
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