HI, I have written some code to generate the layout of a p-cell high-voltage transistor. All shapes created are rectangles (like the active, contact, metal layers). While measuring the devices it was found that the break-down voltage was really low, much lower than anticipated. One of the solutions that has already been tested, and has been proven to be very effective, is to create rounded corners for some of the layers involved. The layouts to test this were all generated manually. No it is my task to put that (rounding the corners) in the p-cell. Is there an easy solution to convert a rectangle in a rounded-corner rectangle? Something like this already exists in Cadence as a SKILL procedure? If not I just have to come-up with something clever myself... With kind regards, Sjoerd
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