Dear wangyunxin, [quote userid="616638" url="~/cadence_technology_forums/f/mixed-signal-design/58539/how-to-set-a-parameter-in-a-verilog-module-as-a-variable-and-send-it-to-the-ade-explorer-to-scan-its-different-values-in-simulation"]I named the parameter k in Verilog as ki, and gave it four different parameter values in the simulation: 20'b00000100000000000000, 20'b00001000000000000000, 20'b00010000000000000000, 20'b00100000000000000000, 20'b01000000000000000000. I wanted to see the simulation results of the circuit system under these four parameters, but ADE reported the following error. How can I solve this?[/quote] First of all, you mentioned changing the variable ki to 4 values,, but then listed five string values. I assume you intended to change it to each of the 5 values? If so, have you tried changing your definition of variable to ki to: strcat(" 20'b00000100000000000000" " 20'b00001000000000000000" "20'b00010000000000000000" "20'b00100000000000000000" "20'b01000000000000000000") You may need to escape the single quotation mark you included in the string, but I am not sure and am unable to test the expression. Shawn
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