Hello, everyone! I am currently designing a amplifier for the multiplying dac (MDAC) for the pipeline ADC. The circuit diagram is show in Fig. 1. This circuit operates in two clock phases: phi1 and phi2. In phi1, the amplifier is auto-zeroing and its offset will be sampled in capacitor Cc. Vin is sampled in C1 and C2. In phi2, the amplifier will do the amplification. Clearly, the feedback factor of the amplifier in phi1 and phi2 is different. So I want to simulation the loop gain in phi1 and phi2 separately and also want to see the effect of different feedback factors. Since this circuit is a discrete time circuit, it seems that I should use PSS analysis to find its operation point and do the small signal analysis to analysis the loop gain. I also found a slide in the internet to teach how to use the PSS+PSTB simulation to analysis the loop gain of switched capacitor CMFB. The link is lumerink.com/.../Loop%20Stability%20Analysis.pdf However, I have a question about the method using in this slide. For better description, pls see Fig. 2 (actually page 28 of the slide). The SC CMFB also operates in two clock phases. The feedback capacitor of the CMFB circuit is different is each phase. So the question is how can the PSS analysis distinguish two clock phases and PSTB simulation results is corresponding to which clock phase? So I want to make a clear statement of my question: How to use PSS+PSTB or PSS+PAC to simulation the loop gain in each clock phase Fig. 1 Fig. 2
↧