Forum Post: MOSFET dimension in schematic and LVS mismatch in TSMC 180nm I/O library

I am using an analog I/O pad library from TSMC180nm. The schematic view is imported from a Spice file. The layout is from a GDS file. I attached an example of a pmos showing this issue. In the schematic view, the l and w are set to 0.4u and 54u to match the dimensions in the layout. However, the dimensions become other numbers when running LVS therefore giving LVS errors. If I change the dimensions in the schematic, the numbers shown in LVS will also change, but they never match the numbers in the schematic. Any help is appreciated!