Below is showing my Master.v ******************************************************************************************************************************************************************************************************************** ///////ALU module ALU ( input [31:0] A,B, input[3:0] alu_control, output reg [31:0] alu_result, output reg zero_flag ); always @(*) begin // Operating based on control input case(alu_control) 4'b0001: alu_result = A+B; 4'b0010: alu_result = A-B; 4'b0011: alu_result = A*B; 4'b0100: alu_result = A|B; 4'b0101: alu_result = A&B; 4'b0110: alu_result = A^B; 4'b0111: alu_result = ~B; 4'b1000: alu_result = A >B; 4'b1010: begin if(A 0x00940333 Memory[3] = 8'b0000_0000; Memory[2] = 8'b0000_0001; Memory[1] = 8'b0111_1100; Memory[0] = 8'b0000_0001; // Setting 32-bit instruction: sub t2, s2, s3 => 0x413903b3 Memory[7] = 8'b0000_0000; Memory[6] = 8'b0000_0110; Memory[5] = 8'b1000_1111; Memory[4] = 8'b1110_0010; // Setting 32-bit instruction: mul t0, s4, s5 => 0x035a02b3 Memory[11] = 8'b0000_0000; Memory[10] = 8'b0000_0101; Memory[9] = 8'b0111_1100; Memory[8] = 8'b0000_0011; // Setting 32-bit instruction: or t3, s6, s7 => 0x017b4e33 Memory[15] = 8'b1111_1111; Memory[14] = 8'b1111_0100; Memory[13] = 8'b1010_0000; Memory[12] = 8'b1010_0100; // Setting 32-bit instruction: and Memory[19] = 8'b0000_0000; Memory[18] = 8'b0010_1001; Memory[17] = 8'b0001_1101; Memory[16] = 8'b0010_0101; // Setting 32-bit instruction: xor Memory[23] = 8'b0000_0000; Memory[22] = 8'b0001_1000; Memory[21] = 8'b0000_1101; Memory[20] = 8'b0110_0110; // Setting 32-bit instruction: not Memory[27] = 8'b0000_0000; Memory[26] = 8'b0010_1001; Memory[25] = 8'b0011_1101; Memory[24] = 8'b1100_0111; // Setting 32-bit instruction: shift left Memory[31] = 8'b0000_0000; Memory[30] = 8'b0101_0111; Memory[29] = 8'b1100_0110; Memory[28] = 8'b0000_1000; // Setting 32-bit instruction: shift right Memory[35] = 8'b0000_0000; Memory[34] = 8'b0110_1010; Memory[33] = 8'b1101_0010; Memory[32] = 8'b0111_1001; /// Setting 32-bit instruction: Campare Memory[39] = 8'b0000_0000; Memory[38] = 8'b0111_1010; Memory[37] = 8'b1101_0010; Memory[36] = 8'b0110_1010; /// Setting 32-bit instruction: Memory[43] = 8'b0000_0000; Memory[42] = 8'b0111_0111; Memory[41] = 8'b1101_0010; Memory[40] = 8'b0111_0010; end endmodule //IFU /* The instruction fetch unit has clock and reset pins as input and 32-bit instruction code as output. Internally the block has Instruction Memory, Program Counter(P.C) and an adder to increment counter by 4, on every positive clock edge. */ module IFU( input clock,reset, output [31:0] Instruction_Code ); reg [31:0] PC = 32'b0; // 32-bit program counter is initialized to zero always @(posedge clock, posedge reset) begin if(reset == 1) //If reset is one, clear the program counter PC report/HDL_min_Netlist.v write_sdc > report/constraints.sdc write_script > report/synthesis.g report_timing > report/synthesis_timing_report.rep report_power > report/synthesis_power_report.rep report_gates > report/synthesis_cell_report.rep report_area > report/synthesis_area_report.rep gui_show ********************************************** WHEN I COMPARING MY GOLDEN.V WITH HDL_min_Netlist.v during conformal , I got these non-equivalent point for every reg memory and for every data memory. I don't know what to do with these non-equivalent point. I've been stuck here for the past four days. Please help me in this and how can I remove this non- equivalent point , since I am new to this I really don't know what to do.
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