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Forum Post: RE: MOSFET dimension in schematic and LVS mismatch in TSMC 180nm I/O library

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Looks like the schematic netlist might be in error. Check the netlist. What values are present? Are parallel devices merged? Check CDF for auCdl netlisting. W/L might not netlist the values as you see on the form. Why not LVS against the source spice?

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