Hi, I am trying to synthesize a relatively large design (consuming ~56mm^2) using Cadence genus211_21.15. Design involves many gate-level operations and I'm using already generated netlists as submodules (by reading them using "read_netlist") to speedup the synthesis runtime. I also use "preserve" and "ungroup" to further improve synthesis time. This indeed improves the synthesis time significantly. However, netlist generation (write_hdl) takes very very long time. For a smaller design, the same approaches finished the synthesis in ~30 minutes; however, netlist generation took 3 days! (The size of final netlist verilog file is only 600KB). Did anyone face similar issue? I'll appreciate any suggestion to solve this issue. Thanks.
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