I'm unsure what you're trying to do with the assigns. However, this code does work without error: module inst; logic a; endmodule module test; generate genvar i; for(i=0; i<2; i++) begin : acc inst inst (); end endgenerate assign acc[0].inst.a = acc[1].inst.a; //assign acc[1].inst.a = out[0]; // This comes as an output from acc[0].insta.out endmodule Tim
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