Forum Post: RE: Import verilog with VDD, VSS, VNW & VPW

Hi Volker, Thank you for your response. By " VDD, VSS, VNW & VPW ports are unconnected in the schematic view " I indeed mean the pins are missing, which is normal for digital flow as verilog functional view does not have those pins defined. However, for AMS simulations with synthesized schematic, I need to add those connections. As far as inherited nets are concerned, I see VDD and VSS defined as inherited nets in the standard cells but VNW and VPW are not defined as inherited nets. So, the main query is how to define connections to VNW and VPW at top level.