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Forum Post: RE: Simulation with verilog-a model

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It's because the magnitude of the integral part is tiny in your example because of the higher frequency of the sine wave. If you plot just I2:r1 (and not I2:R on the same graph) you'll still see the sinusoidal variation and it has the correct phase relationship with the input voltage to show it's an integral. However, the integral is only 1n peak to peak, whereas in my example (with 1kHz rather than 500MHz) it has ~300u peak to peak. So the idt is very small variation on top of the 25M value that comes from rin in the equation for r1. Andrew.

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