Forum Post: Wiring Assistant table filler
Hi, (Cadence version: IC 6.1.8.500.8) I am trying to make a small script that would automatically fill in some fields of the Wiring Assistant and then create presets (this part is working), but still...
View ArticleForum Post: RE: How to fix "*WARNING* file /home/Kaveri/CDS.log Malformed...
Hi Andrew, Thank you very much for the prompt reply. Best regards, Marben
View ArticleForum Post: RE: Compare the database footprint with library footprint -Skill
This biggest issue with the footprint mechanism of Cadence is that the padstack figure data is not taken from the PSM but from the actual padstack files. You can test this, t ry to place a PSM file...
View ArticleForum Post: Invisible Power Pins on Parts B, C., . . . in Multiple Package Parts
I have created a schematic symbol in Capture 16.6 for an op-amp package that has an exposed die pad (EP). I would like to have the V+, V-, and EP appear on package A only, and not package B. When I...
View ArticleForum Post: RE: Invisible Power Pins on Parts B, C., . . . in Multiple...
If you have selected the option of homogenous while designing the symbol then 5 pins will appear in both parts. Go for a heterogeneous package and define the power pins and IO in part A and rest in part B
View ArticleForum Post: RE: Power Integrity
Hello Manvir, I'm a student at The University of Pennsylvania (Department of Electrical and System Engineering) and we're working on the lab projects with Cadence Alegro. Could you please resend the...
View ArticleForum Post: DRC Error Marks
Hi all, I am proceeding a schematic design of my project. I found a net didn' t connet to the signal port on hierarchy block, i.e., it just connected on the frame of the hierarchy block. But the DRC...
View ArticleForum Post: RE: Invisible Power Pins on Parts B, C., . . . in Multiple...
Thanks, Avenger Thanos. This approach worked fine, and I can forge ahead. However, I would still like to understand how the original part, which was defined as homogeneous, managed to have the two pins...
View ArticleForum Post: RE: DRC Error Marks
You need to turn on the DRC checks under Rule Setup - check for hierarchical port connection. (This is w.r.t SPB 17.4 OrCAD Capture)
View ArticleForum Post: RE: Wiring Assistant table filler
You confuse a symbol and the actual form behind it (It is tricky because the CIW displays them the same way) deFindAssistant("Wire Assistant" hiGetCurrentWindow())->hiHandle actually gives you what...
View ArticleForum Post: RE: "File Open" and "Save As" in SKILL
Hi everyone! I want to ask if I can turn the window 'Save as' on? I can not find any function to do that. Such as axlDMFileSaveAs for example. Please help me. Thank you. Luan.
View ArticleForum Post: RE: Wiring Assistant table filler
I just gave it a try and it does exactly what I was hoping for. Thank You very much!
View ArticleForum Post: RE: hiDisplayForm issue
Hi, It will be really hard to help you without your code or at least further explanation? What is / contains the code.il file you are talking about? Actually the error is pretty clear, it seems you are...
View ArticleForum Post: Pin placement does not show up
Hi Cadence Forum, I have a large amount of pins 4000+, and I want to generate pins and attach them to the corresponding nets automatically. I want to use Place -> Pin Placement, but for some reason...
View ArticleForum Post: RE: Pin placement does not show up
Hi Nicolas, Please contact customer support over this. Andrew.
View ArticleForum Post: RE: rod PCELL (Metal with slot)
Hi All, I need to have a slot with diagonal corners. What do you suggest to do in this case? Thanks. Alessandra
View ArticleForum Post: Nested for loop
A=list( (1 2) (6 2) (8 2) (5 2) (7 2) (3 2) ) B=list( (8 10) (3 10) (1 10) (5 10) (7 10) (6 10) ) I want to have a list C, whose 1st element from A matches the 1st element in B and make a list like the...
View ArticleForum Post: Saving design image to file with instances in virtuoso with SKILL
Hey everyone, I'm seeing a bit of undesired behavior (for my particular use, it might make sense in general) when using the hiExportImage command. When the image saves to file it has the outlines of...
View ArticleForum Post: RE: Nested for loop
C=foreach(mapcar elem1 A list( elem1 car(exists(elem2 B car(elem1)==car(elem2))) ) ) Andrew
View ArticleForum Post: RE: rod PCELL (Metal with slot)
As outlined in the forum guidelines , please don't post on the end of an old thread with a new topic such as this (even if it's somewhat related to the old thread). So please start a new thread, with...
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