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Forum Post: RE: Countersink Holes and Drill File

Updating to the latest version did the trick. Now the software is creating the new file "MyBoard-cd-TOP.drl" with the countersink drill information. Thanks...

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Forum Post: RE: Plotting temperature in a transient simulation

Look in the results browser, under the "tran" results. At the top level you should now see a signal called "temp" which you can plot. Andrew.

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Forum Post: RE: Plotting temperature in a transient simulation

that is exactly where i am looking, and there is no "temp" to plot, there are all my signals etc, but nothing "temp" related. did i miss some intermediate step maybe?

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Forum Post: RE: Plotting temperature in a transient simulation

Alright i found my problem...i did it for default "nominal" corner, but im running some custom corners, all i had to do is add that file definition in the specific corner im running. nevermind, now...

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Forum Post: Smooth dynamic parameter variation in transient sim

In a transient sim we know we can put any PWL source and if we define t1 and t2 with their corresponding values, during a sim there will be linear transition of the voltage source between that time. if...

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Forum Post: RE: Plotting temperature in a transient simulation

I realised after my previous post (I had a personal commitment this evening so couldn't reply sooner) that you might have been using corners in ADE XL and so the Setup->Model Libraries on the test...

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Forum Post: RE: Plotting temperature in a transient simulation

great, thanks a lot! noted.

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Forum Post: RE: Smooth dynamic parameter variation in transient sim

There's no way to do it completely linearly, but you can do it in small discrete steps without having to define all the individual steps by using the param_step parameter (see "spectre -h tran") which...

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Forum Post: RE: hiDisplayForm issue

One more quick question. I am trying to send list to the function that reads symbol then converts to SymboltoString, so when I tried to send values through the list, it is not reading it. Is there a...

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Forum Post: RE: hiDisplayForm issue

Your question doesn’t make any sense - I cannot work out from your question what you’re doing, what doesn’t work or what you actually want it to do. Please provide some code which shows the issue. Andrew

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Forum Post: Bus routing in Allegro PCB Designer

Hello, i am a student studying allegro pcb designer. I have trouble in routing a bus. I think all of channels in a "bus" must have same( or very similar) characteristics so that they must be routed in...

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Forum Post: Method to scale up or down lots of resistor/capacitor value together

Hi, I encounter such a user case: I have large number of capacitors and resistors in one schematic, each with a specific capacitance or resistance value. Now I want to scale up all capacitance by X...

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Forum Post: RE: Help for a beginner in Allegro PCB please.

Hi, can you share the tasks with the connectors please? I need to practice before my probation period as an intern in Electronic PCB Design or Embedded System Design at I will work with Prof. Julius...

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Forum Post: Unable to find the class and subclass of teardrops

I am using the latest version of OrCAD PCB Professional 17.4 S004. I have added a few teardrops in the design. when I try to select them they aren't getting selected I tried various application modes,...

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Forum Post: RE: Bus routing in Allegro PCB Designer

BUS is a collection of nets. Cadence PCB tools have made PCB routing very easy over the years. select the group of nets - add connect and you can route them (it is called group routing)

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Forum Post: RE: Nested for loop

What about if i swap x and y like this: A=list( (2 1) (2 6) (2 8) (2 5) (2 7) (2 3) ) B=list( (10 8) (10 3) (10 1) (10 5) (10 7) (10 6) ) and want to have a list C, whose 2nd element from A matches the...

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Forum Post: RE: Nested for loop

Hi Leo, Very similar - it's just that the elements being compared change - so here using cadr rather than car to get the second elements in the lists. C=foreach(mapcar elem1 A list( elem1...

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Forum Post: About modus design constraints

Hi! In my design, there is an one hold violation on scan path, test data is corrupted during scan cycles (when i run verilog simulation of test vectors). I created constraint 'falsepath' to 'TI' input...

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Forum Post: How to use POWERDC .SUBCKT in PSPICE simulation

Hello, I have exracted a resistance network that models one trace on my PCB with PowerDC. The result is a .ckt file that contains a spice subcircuit with 12 ports. How can I use this subcircuit in a...

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Forum Post: How To Change Library Path In OrCAD Capture 17.4

Hello, I downloaded the symbol and footprint of a part from Ultra Librarian to a local folder. After I put the part in the schematic there is a warning as below. WARNING(ORCAP-2434): Footprint...

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