Forum Post: RE: PCB panelization in orcad pcb designer standard 17.4
The only real option you have is to create a new subclass (Setup - More - Subclasses, panel for example) and then copy the Design_Outline to that layer. Then use the drafting Utilities (Manufacture -...
View ArticleForum Post: RE: Select Outside of box
In the color dialog box enable all colors so that you can find where the objects are then, in general edit enable all items under the find filter. With these settings drag a window for selection and...
View ArticleForum Post: RE: PCB panelization in orcad pcb designer standard 17.4
steve I guess it should be OrCAD Panel editor, not OrCAD Doc editor
View ArticleForum Post: RE: Orcad Capture CIS Design Sync
Save the design after performing sync so that next time it would show you the changes list.
View ArticleForum Post: RE: Allegro - Check for symbols with changed definition
Ohh Great... haven't come across that. Does it also report on IPC rules failure kind of thing?
View ArticleForum Post: RE: Select Outside of box
Thanks for your reply. I already tried this, even when I turn everything on the workspace is so huge that I have to zoom waaaaaay out and you can't see anything. I select around the edges even though...
View ArticleForum Post: RE: Allegro - Check for symbols with changed definition
No just compares version ID on each symbol v the symbol checked into EDM.
View ArticleForum Post: Simulation of gate leakage current using cadence
Hi, all I'm going to test the gate leakage current in TSMC 180nm process. I connect a DC voltage to the gate of an NMOS transistor, and do DC(and tran) simulation, the results of Ig is nan. I'd like...
View ArticleForum Post: RE: Orcad Capture CIS Design Sync
Sorry I cannot get your point. You have meant to say that after the Design Sync command, I have to save the *.dsn design, so that it updates the current changes. Am I get your point?
View ArticleForum Post: Allegro 17.4 Analysis Workflow
Question about Allegro 17.4 Analysis Workflow. Before a certain hotfix (it seems to be up to 11 or 14), the diff. pair impedance analysis worked without problems, now when starting the analysis, it is...
View ArticleForum Post: RE: Simulation of gate leakage current using cadence
Dear Minghao, I don't think I fully understand your simulation. What are the drain, bulk, and source nodes connected to during your DC and transient simulations? What temperature are you running your...
View ArticleForum Post: PSS failure for a ring VCO
Hi Andrew/Shawn, I am doing a post-layout PSS+PNOISE for a 5-GHz 4-stage pseudo-differential ring oscillator . I tried, forcing complementary signals (ring-top voltage and VSS) to one of the ring...
View ArticleForum Post: RE: Select Outside of box
I just wrote a simple skill routine to do this, the skill is shown below: procedure(DelAllOutsideBox() let(() (axlSetFindFilter ?enabled list("all" "nodrcs" "invisible") ?onButtons list("all"...
View ArticleForum Post: RE: Select Outside of box
I couldn't get this to work. I create a file in my env folder called delallout.il and copied this into it procedure(DelAllOutsideBox() let(() (axlSetFindFilter ?enabled list("all" "nodrcs"...
View ArticleForum Post: RE: Select Outside of box
Ah I did get it to work by then typing in skill DelAllOutsideBox() I was also able to re-size my workspace too. Thank you!
View ArticleForum Post: RE: PSS failure for a ring VCO
Dear Subhadeep, Thank you for the detailed description of your design and methodology - I found your description quite useful! [quote userid="504413"...
View ArticleForum Post: xmsim/BSSXCD = The element count of bit-stream has reached to a...
Hi Here is my issue: I have regenerated the register bank and register map for the updated xml (New registers have been added). The compilation is clean but when I run the simulation, it halts at ZERO...
View ArticleForum Post: Skill File need for custom Grid
Hi Folks, I would like to use some skill file for my PCB layout, I know there are many skill files. But need specific skill for 1) Placement Grid 2) Via grid 3) Routing grid through menu bar I have...
View ArticleForum Post: RE: Allegro 17.4 Analysis Workflow
The required components are now distributed and maintained through the Sigrity 2021 installation for PCB Editor 17.4, as they were previously by Sigrity 2019 installation for 17.4. Previously...
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