Forum Post: RE: Matlab Error When Starting from Assembler
Hi Andrew, Thanks for the reply. We're using ICADVM20.1-64b.500.20. Our Matlab version is 2018b. However, checking the process command line made me realize, our tools are bsub'd out to different...
View ArticleForum Post: RE: Virtuoso License Issue: status code -5.
Paulo, Not sure why you're using the base release of an older version. There were some fairly significant changes in IC6.1.7 because of the introduction of ADE Explorer and Assembler, and you're using...
View ArticleForum Post: RE: Way to automatically print the noise summary after noise...
Dear sidm, [quote userid="474751" url="~/cadence_technology_forums/f/custom-ic-design/49603/way-to-automatically-print-the-noise-summary-after-noise-analysis"]Is there a way to automatically print the...
View ArticleForum Post: RE: 2 names on the same net
HI, If you need to connect two different nets then that can be done with a zero ohm resistor. This does not mean the pads on the resistor are joined together with a trace. "There Not" , The physical...
View ArticleForum Post: Testbench for THD and IIP3 simulations
Dear all, I plan to simulate THD and extract IIP3 of a single transistor by using PSS and PSS+PAC analysis in cadence. I have used the testbench attached below to run simulations. Two bias tees are...
View ArticleForum Post: Where can I download user guides for PCB simulation?
Hi, I use PCB SI, and try to simulation using PCB SI. So I download the Allegro PCB SI User Guide(ver.16.6). But there are many other documents to get a detail information. (ex. Allegro SI SigWave...
View ArticleForum Post: RE: Where can I download user guides for PCB simulation?
To access cadence Internet Learning Series courses, log into https://Support.Cadence.com Click on >Learning at the top, then >Online Courses on the left. Type PCB SI in the search bar. Another...
View ArticleForum Post: RE: Testbench for THD and IIP3 simulations
Dear Hossein, [quote userid="486079" url="~/cadence_technology_forums/f/custom-ic-design/49604/testbench-for-thd-and-iip3-simulations"]Are these testbenches correct or I have done something wrong...
View ArticleForum Post: RE: Testbench for THD and IIP3 simulations
Hi Shawn, Thank you for your answer. I am running the PSS simulation by sweeping the amplitude of the input signal (Vac) to plot THD vs Vac (dBm) for the device under test. The frequency is frf=1KHz...
View ArticleForum Post: outline modification
hello: i am trying to enlarge the substrate size using the existing design file. but i am getting an error saying "pick is outside the extent of the drawing." can i make the substrate outline larger?
View ArticleForum Post: RE: auCdl Netlist LVS Naming Conflict
Thank you for the reply, adding the linked procedure to the .simrc file fixes this problem.
View ArticleForum Post: RE: Run Options of ADE Assembler in Cadence Virtuoso
Dear Shawn Thank you once again, I read both of the comments and indeed it boosted my MC simulation time and made advantages of the parallel simulation in multi multi-run I do appreciate your both...
View ArticleForum Post: RE: Use if statement to define parameters in Monte Carlo simulation
Just to give a little update on this topic - in SPECTRE20.1 ISR12 (released recently) there's a new distribution type sunif which stands for set-uniform or discrete-uniform. More can be found out...
View ArticleForum Post: RE: cdsenv variables
Hi Andrew, Sorry for the late response Thanks for your anwser, I will use the integration part Sadly the cdsenv variables don't have a regular documentation structure just as I feared Have a nice day...
View ArticleForum Post: How to group objects in schematic or add data
Hi, I have a skill that adds a lot of objects to a schematic (instances, wires, and wire labels ) I am looking for a way to delete all added objects later. One option would be to create some group...
View ArticleForum Post: IC 6.1.7 on RHEL8
Hello all, I was wondering if someone could tell me if Cadence IC 6.1.7 works on a RHEL 8 machine. I have it working on CentOS7, but when i try to launch virtuoso from RHEL8, I get the following...
View ArticleForum Post: RE: IC 6.1.7 on RHEL8
David, It's definitely not supported on RHEL8, but of course there may be a way of making it work (but no testing would have been done). I just located an RHEL8 machine and tried running, but I see...
View ArticleForum Post: RE: How to group objects in schematic or add data
There's two kinds of groups in the database - groups and figGroups. groups are for creating groups of objects (which don't necessarily have to be selectable figures - they can be logical objects like...
View ArticleForum Post: RE: Highlighting the NET
I modified your code as shown below: procedure(chknet() let((Net_Get_List dbid) axlClearSelSet() axlSetFindFilter(?enabled '("NOALL" "NETS") ?onButtons "NETS") (Net_Get_List =...
View ArticleForum Post: RE: outline enlargement
You may need to increase the Design Extents values for Left X and Lower Y and and also increase the Width and Height to allow the new outline to fit...
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