Forum Post: RE: How to obtain Discrete-Time (DT) response from a switched-cap...
Dear Frank, Just very quickly to the point difference "Spectrum of sampled signal" and "PAC sampled": You wrote: “ Ok, a better formulation would be: "The sampled PAC analysis samples the output...
View ArticleForum Post: RE: How to obtain Discrete-Time (DT) response from a switched-cap...
The problem I see with your approach is that you are trying to simulate all input frequencies at once and are going beyond the Nyquist frequency of the circuit at the same time. A sine at the input of...
View ArticleForum Post: RE: PVS requires pin Label to pass the LVS
Dear Andrew, Thank you very much for your help, that was a useful solution and covered my inquiry Best Regards
View ArticleForum Post: LVS complaining about lower level hierarchal design
Hello, I am at the chip level verification when the Assura LVS started to complain about mismatching in the lower level hierarchal design. To make it clear my highest chip-level design has four blocks...
View ArticleForum Post: Change drawing origin function not working
Hi Guys, my "change drawing origin" is not function well. It pop up "Edit>Change" function. Anyone have solution for this?
View ArticleForum Post: RE: How to use calculator in ADE Explorer
Thank you Andrew. I found a option of "send to calculator" is in right-click menu. BTW, nice new profile photo
View ArticleForum Post: double counting of MOM capacitors in extracted view
Hi, I use Calibre for LVS and QRC for parasitic extraction. As it turns out, this results in double counting of MOM capacitors. QRC treats them as parasitcs and at the same time mom capacitor cells...
View ArticleForum Post: Cell copy problem with layout view in Cadence Virtuoso
Hello, I am facing a problem when I copy some of my cells that has layout view. That is when I work on the layout of the copied cell it still modifies the original one and caused me a lot of troubles...
View ArticleForum Post: PCB Editor 17.4 summary description in form
Can anyone help me that how can I add this summary description in my form using skill code in Allegro 17.4. This summary description becomes visible when I hover on any option. Thanks
View ArticleForum Post: RE: How to obtain Discrete-Time (DT) response from a switched-cap...
Dear Frank, Aaahhhhhhhh, Yeeeesssssssss, clear!! How easy! As you proposed, I will check with 1 freq. at a time only. ( I would like to also do this freq. sweep automatically, but for this, I would...
View ArticleForum Post: RE: How to export design data to csv format
Hi, I have no access to this dialog box with Orcad CIS 17.2-2016 S079, is it possible only with Orcad 17.4 ? Thanks, Thierry
View ArticleForum Post: RE: How to export design data to csv format
Upgrade to latest hotfix. It should work in SPB 17.2 as well.
View ArticleForum Post: RE: OrCAD capture Page Numbering
You need to "pack" the values with zeros to get the sort, like 001, 002 ... 009, 010, 011 ... 099, 100, 101 and so on. The sorting relies on some Microsoft functionality which never implemented...
View ArticleForum Post: RE: Change drawing origin function not working
Which exact version are you running? It may be possible that this function isn't correctly implemented in the version that you are running, or you may be trying to set an origin that isn't possible...
View ArticleForum Post: Possible to edit new schematic symbol template ?
Is it possible to edit the default template for creating a new part in a library ? Every time one creates a new part in a library , one has manually add ones own custom part properties. This process...
View ArticleForum Post: RE: How to obtain Discrete-Time (DT) response from a switched-cap...
[quote userid="538772" url="~/cadence_technology_forums/f/custom-ic-design/51410/how-to-obtain-discrete-time-dt-response-from-a-switched-cap-sc-circuit-integrator/1383204#1383204"] Is there maybe...
View ArticleForum Post: RE: Change drawing origin function not working
i am using "Orcad PCB Designer Professional v17.2. the method you mentioned is working fine. But it is better with "Change Drawing Origin" function where origin can be assign by mouse clicking....
View ArticleForum Post: Netlist Power Analysis Flow with RTL Stimulus
Hi all, I am exploring Joules for the power analysis of a netlist synthesized with Genus. Eventually I want to plot the power activity of a stimulus along with the frames. The .vcd is parsed with the...
View ArticleForum Post: Netlist Power Analysis Flow with RTL Stimulus
Hi all, I am exploring Joules for the power analysis of a netlist synthesized with Genus. Eventually I want to plot the power activity of a stimulus along with the frames. The .vcd is parsed with the...
View ArticleForum Post: RE: ORCAP-1589: Net has two or more aliases that might lead to a...
You could make a PCB shunt symbol to connect those two nets together. Shouldn't both wires have the same net name (alias) in first place anyways ?
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