Forum Post: Site CORE doesn't exist in the search path
Hello all, I am importing my design from Encounter13 to Virtuoso (IC.5) in order to apply DRC and LVS checks by Calibre. But before 'streaming in' my design, I imported the LEF files. In icfb, when I...
View ArticleForum Post: RE: Unbound pins when running Assura LVS in Virtuoso Layout Suite L
I solved it! Instead of creating PINs, I just had to create Labels in the PIN layer (MET1 purpose) . This way, I have successfully extracted the schematic from the layout. Thanks for your help! David.
View ArticleForum Post: Without mechanical net-shot
We use dual power options in our board. Able to connect two power in one via like below image. Please advise any option. Without mechanical net-shot.
View ArticleForum Post: RE: skill code to toggle waveform visibility
Hi Dan, Currently there isn't really a SKILL API to do this (certainly nothing public, and even amongst the private stuff it isn't really quite what you're after). I have an outstanding action to make...
View ArticleForum Post: RE: Site CORE doesn't exist in the search path
Well, I found the reason. I just uncommented the statment "NAMECASESENSIUTIVE ON" in the lef file, to avoid the following warning. WARNING (LEFPARS-2007): NAMECASESENSITIVE state is obsolete in version...
View ArticleForum Post: RE: skill code to toggle waveform visibility
Thanks for the quick reply. I'm not surprised that currently I can't quite get there from here. There seemed to be too many gaps. I'll look forward to something in the future. BTW, if you'd like some...
View ArticleForum Post: RE: How to use AXL function
Start by reading the Skill Language User Guide. ...\doc\sklanguser\sklanguser.pdf
View ArticleForum Post: skills & script in allegro 16.6 viewer.
Hi, Abled to run skills & script in allegro 16.6 viewer. Thanks Prakash.S
View ArticleForum Post: RE: Marking nets in cadence showing shorts
HI Marc, I have poly resistors in my layout. But since LVS is going clean there can't be any shorts. Also i have disabled M1-PO and M1-OD connections in mark net option. I didn't get your second point,...
View ArticleForum Post: RE: Marking nets in cadence showing shorts
HI Dan I am using Layout XL only. annotation browser and navigator is not showing any shorts and also LVS went clean .In my layout VDD and VSS are showing as shorts, so i am not sure where to begin...
View ArticleForum Post: RE: Marking nets in cadence showing shorts
Hi Anand, MarkNet is not an extraction tool. It wont detect/extract devices. So being LVS clean does not have any meaning for MarkNet. Like I said, MarkNet nly knows the layeer stack: Poly Cut M1 Via1...
View ArticleForum Post: Create a block of components for PCB placement and routing reuse
I know this has been asked for previous versions of Allegro. But can anyone suggest the flow methods for design block reuse please. The blocks would be in both schematic Design Entry and Allegro...
View ArticleForum Post: Exporting ADE-L Variables
Dear all, I have an ADE-L session which has some variables defined and I would like to export them so they could be used in a script (tcl script). Is there a simple way of doing it ? Best regards, José...
View ArticleForum Post: RE: Error SPCOCN-3315
Solved. For reference, the issue was with two files located in the sch_1 project folder. A colleague had accidentally changed the permissions of the *.xcon and *.dcf files so that my computer was not...
View ArticleForum Post: RE: Create a block of components for PCB placement and routing reuse
Yes it's easy and yes it uses a hierarchical element. Take a look at \doc\pcbflows\pcbflows.pdf which goes through this. ( = C:\Cadence\SPB_16.6)
View ArticleForum Post: RE: Create a block of components for PCB placement and routing reuse
Hello Steve, Thank you for this reply. I just looked in my pcbflows directory and noticed the SPB16.6 directory has a pdf that says it is Product Version 16.5 and not 16.6-2015. Is this the correct...
View ArticleForum Post: RE: Create a block of components for PCB placement and routing reuse
Yes that's fine. Cadence don't always update the documentation every time there is a release. Normally only if something changes.
View ArticleForum Post: RE: Running 2 procedures or function in 1 bindkey
Hi, This is good but I have one small correction: the ~> operator should be used with database objects such as cellview id's, object id's, tech file id's, rod objects and so on, whereas the ->...
View ArticleForum Post: RE: Running 2 procedures or function in 1 bindkey
Hi Lawrence, Whilst I tend to follow the convention you suggest (although generally speaking I write in LISP syntax rather than using operators at all, as you know), strictly speaking the only...
View ArticleForum Post: stb and tran analysis discrepancy
I'm having trouble understanding the results of a stb simulation I'm running over process corners and temperature for a basic switched capacitor active integrator. There is a low frequency pole due to...
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