Forum Post: Challenge 6 - simulation has failed: Error: residual of Mass is...
I can´t complete the simulation due to this problem. Not sure where the mistake is?
View ArticleForum Post: RE: Functional coverage: array of covergroups
Late to the party here, but just in case somebody stumbles upon this. To enable per instance collection, you need to add "option.per_instance = 1;" to your covergroup. Otherwise, all gets collected...
View ArticleForum Post: RE: Regarding MOSFET size problem ("Edit Instance Properties") in...
Hi Andrew, As you mentioned the skill directory, I found a folder named "skill" in the installed pdk directory. Making all the files of that folder executable solved the problem, now I'm able to run...
View ArticleForum Post: RE: ADE corner setup: Can I define a parametric set there?
And there's a long-standing request (with a growing number of duplicates) asking for native support for paramsets within the corner definition - the master CCR number is 1295169. Andrew
View ArticleForum Post: RE: Plotting with corners as x-axis.
It works when I zoom in, but that way I cannot see the complete plot, obviously. I use Virtuoso IC6.1.8-64b.500.14 If VIVA has its own version, I would like to know where I can see it.
View ArticleForum Post: RE: Constraining some nets to route through a specific metal...
Hi Riya, did you manage to get access to support.cadence.com ? If you have not yet, I suggest you to do so, because there are many articles you can refer to for help. To guide the router, you can set...
View ArticleForum Post: RE: Capture 17.4 - Allegro properties no longer available in...
That fixed it. Thanks!
View ArticleForum Post: RE: What areas of OrCAD Capture would users like to see improved?
Most of the Capture options have incredibly unhelpful names/descriptions. Some of them do unpredictable and catastrophic things. Symbol Editor is crusty and slow. Quality of life is horrible if you...
View ArticleForum Post: Jaspergold -- Net does not have a driver
Hi In Jasper gold >>>Even after assuming a value for the declared signal --- Seeing warning as net "signal name" does not have a driver ex_signal[4] ---> ex_signal[0] ,ex_signal[1],...
View ArticleForum Post: RE: What areas of OrCAD Capture would users like to see improved?
Make it easier to update the symbol or footprint of a CIS part already in a schematic with an alternate symbol or footprint. Currently this has to be done through Part Manager -> Link Database...
View ArticleForum Post: License check has failed
Hello, I wasn't able to open Omnis today in reason of a failed license check. As you can see in the first screenshot , the program ask me to reactivate my license. I tried to do it again with the...
View ArticleForum Post: Mistake in Challenge 8
Hallo, In der Challenge 8 steht zwei mal Booster_support_real_wall. Ich denke eins davon sollte die front_wall sein?
View ArticleForum Post: RE: Mistake in Challenge 8
Im Video der Übung wird die rear_wall auf Level 6 verfeinert, die front_wall wird jedoch übersprungen. Dementsprechend denke ich, dass die rear_wall Level 6 und die front_wall wie die Seiten Level 5...
View ArticleForum Post: RE: spectre: save all currents connected to a given node, but...
Dear Zol, [quote userid="570636" url="~/cadence_technology_forums/f/custom-ic-design/56675/spectre-save-all-currents-connected-to-a-given-node-but-exclude-given-connections"] Is there any way to...
View ArticleForum Post: Behavioral model for a VGA
Hello all, I have modelled a Transimpedance amplifier (TIA) using verilogA as a second order low pass filter so that I could observe the effect of gain peaking (by tuning the Q factor). Now, in order...
View ArticleForum Post: RE: What areas of OrCAD Capture would users like to see improved?
[quote userid="380279" url="~/cadence_technology_forums/pcb-design/f/capture-cis/55606/what-areas-of-orcad-capture-would-users-like-to-see-improved/1388146#1388146"]When placing a CIS part, I should be...
View ArticleForum Post: RE: What areas of OrCAD Capture would users like to see improved?
Engineers tend to capture designs on a D-size sheet so they won't have to tangle with off-sheet connectors. I get it. Get the design captured, then structure the schematic for flow and readability. It...
View ArticleForum Post: RE: Behavioral model for a VGA
Dear TUKA, [quote userid="544756" url="~/cadence_technology_forums/f/custom-ic-design/56682/behavioral-model-for-a-vga"]Now, in order to flatten the TIA response, I would like to cascade my TIA with a...
View ArticleForum Post: define variable in scs file
Hi, I would like to create a .scs file, which will be included as a normal model file. The content is section AAA parameters + X=0 + Y=0 + Z=0 endsection X,Y,Z are variable to be defined. I wish their...
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