Forum Post: RE: Net alias label deleted by mistake, howto get it back
Once the net alias is deleted, the tool assigns the system generated net alias internally. You can also check the net name in property editor. Hence in order to have the same net alias again, you need...
View ArticleForum Post: RE: Net alias label deleted by mistake, howto get it back
Hi Akshay khosla, omg now i understood the delete net alias function. in eagle the net name was not dependent on the label, in orcad the net name is also deleted with the symbol, net alias. Thanks!
View ArticleForum Post: RE: The circuit is not giving correct plot for output
M5 shows 'nil' where the other FETs show 'l:60n'. That is likely to cause an issue.
View ArticleForum Post: RE: Tagging uvm_errors in waveform file for post-processing
Hi Antonio, There is a feature in Verisium Debug to send any log file message (not just UVM errors) from its "SmartLog" tool to the waveform, and a waveform trace will be plotted on-the-fly with a...
View ArticleForum Post: Why is Spectre ignoring time tolerance or time step conditions...
Dear community I am using the following Verilog-AMS model to generate sharp pulses: module my_source(MINUS, PLUS); inout MINUS; electrical MINUS; inout PLUS; electrical PLUS; parameter real delay =...
View ArticleForum Post: RE: Tagging uvm_errors in waveform file for post-processing
Hi Doug, Thanks for your reply. I didn't know about Verisium Debug, I'll investigate if we can use it! Does the smartlog tool also annotates the waveform for post-processing, or during live-debugging?...
View ArticleForum Post: RE: DB Doctor 23.1 Download
I am running the Allegro Free Viewer 23.1.2023 P001 [9/29/2023] on windows. I've been searching for a way to install db doctor but it doesn't exist in the tools/bin folder. I have to believe it isn't...
View ArticleForum Post: RE: Why is Spectre ignoring time tolerance or time step...
Whilst I'm not sure this is the right way of solving the problem, the issue is that if you use $bound_step(), you need to invoke it in every iteration and not just at the times of the event -...
View ArticleForum Post: RE: Tagging uvm_errors in waveform file for post-processing
Hi Antonio, Yes, that feature is supported for both post process and interactive debug. It is a feature of Verisium Debug and not supported in SimVision. Thanks. - Doug
View ArticleForum Post: RE: shape splits
i followed the video and found out that i did not have a routein layer set up. i placed a plane on the route keepin layer and it worked. thank u steve. u always helped me a lot.
View ArticleForum Post: RE: how to force the variables inside a class? i'm facing this...
Now I can force on the static variables used in the verification environment.
View ArticleForum Post: RE: shape splits
steve wrote a comment but i could not find it here. someone deleted it?
View ArticleForum Post: RE: how to force the variables inside a class? i'm facing this...
Understood how to use xmhelp. Before this I was using like this " xmhelp FOAUTO" which hasnt worked.
View ArticleForum Post: Single Trace Model in enabled and grayed out while routing the...
I have create a differential pair for 2 nets but while performing the differential pair routing in the PCB editor, the Sigle Trace Model is enabled and i can't uncheck it because the option is grayed...
View ArticleForum Post: RE: Nets in the PCB layout not respecting the spacing rules...
Hai Steve, the problem was the Default rule in the spacing was renamed to other name which was causing the PCB editor tool to not take the value to spacing constraint value, so i had change the name...
View ArticleForum Post: Creating a multiple drill padstack in SKILL with custom pattern
I'm trying to figure out how to create (custom) multiple drill in SKILL. my kung-fu of searching help files and forums may be weak but all i find is referring to 17.2 or older versions. using...
View ArticleForum Post: RE: Single Trace Model in enabled and grayed out while routing...
Single Trace Mode option actually which is grayed out while doing differential pair routing
View ArticleForum Post: RE: Why is Spectre ignoring time tolerance or time step...
Dear Andwer Whilst I totaly agree with you that this might be not the ideal way to tackle to probelm, I can confirm that your proposed solution works. Here are the adjustments of the code for those...
View ArticleForum Post: RE: The circuit is not giving correct plot for output
And: Forcing 20 mA through devices that look like minimum size (W = 200 nm) is unlikely to work...
View ArticleForum Post: Allegro: Tip of the Week : Push Connectivity
At times, there might arise a condition in the design where you need to push the net of selected pins to all its physically connected objects. For example, a few pins are updated with a new net, and...
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