Forum Post: API for adding Calculator Function Categories
Hello: 1. Is there a way to add a calculator function category using a SKILL function rather than by defining them in the "template catalog summary file" 2. Is there a way to define the category when...
View ArticleForum Post: RE: accessing leWeChooseLayerForm
Thanks Andrew for the response. How do I call leHiLayerTap() on a specific point? Is there anything like leLayerTap(?pt enterPoint()) In the end I need to save both the point and LPP -Ramakrishnan
View ArticleForum Post: RE: ERROR (ADE-3023)
Thank you so much Andrew. The problem I get is that my .profile file shows an error at the end when compiling (even before adding the MMSIM, INCISIVE... lines, by the moment I'm writing the variables...
View ArticleForum Post: Compliance current setting in a voltage source.
Hello, I am doing some experiments on-chip using semiconductor analyser, where I can set a compliance current in the voltage source. Now I need to simulate a similar circuit. So, I need a voltage...
View ArticleForum Post: Integration with matlab
Hello, Is it possible to measure a parameter like current or voltage in spectre simulation & take it to matlab real-time where an iteration is performed & it's result is again used to alter few...
View ArticleForum Post: Re-evaluate results with ADEXL
Hello, I can re-run simulations from the terminal after they've bugged for some reason. The corresponding results are then accessible from the results browser, but unfortunatelly when I click on the...
View ArticleForum Post: What's the problem of my custom PCB design using a CC1310 radio?
I have designed a custom PCB using a CC1310 radio, based on the reference design for the CC1310 LaunchPad(datasheet) . The uC is programming, and running code, when I attempt to send data through the...
View ArticleForum Post: RE: Verilog-A: Lookup tables for AC analysis
Thank you Andrew Beckett for the reply. I think I have figured out what was the problem. In practice, the derivation was made recursively to the capacitance and not just to the voltage. I had assumed...
View ArticleForum Post: tie cell net connection missing
Why Tie Cell connections are missing in the instantiated module in the final PNR Verilog netlist, Module declaration in the final netlist has tie cell connections but the instantiated cell doesn't show...
View ArticleForum Post: RE: Integration with matlab
You might want to take a look at https://community.cadence.com/cadence_technology_forums/f/92/t/37406
View ArticleForum Post: RE: how to determine fet pcell actual drawn width per finger?
Sorry for the delay, was out sick for a week. This is 'folding by hand' i.e. modify a generated pcell's properties to increase its finger count. Our pcells do internally calculate w-per-finger based on...
View ArticleForum Post: RE: when are DRD markers refreshed?
I don't see 'Design' in the layout tool Verify banner menu. This is VLS-L IC6.1.7-64b.500.6. The docs point out that it's XL or GXL only. We do have one WANnable XL license somewhere, is there an L way...
View ArticleForum Post: verilog-A file simulation value update to the design variable in...
Hey, I am using few iterations using the verilog-A file in spectre simulation. I have a design variable in ADE-L for a voltage pulse source written using pwlfile. I want that if my iteration in the...
View ArticleForum Post: Help on a simple component symbol definition in PCB Librarian...
Hello everybody, I am trying to define a new part in Part Developer within Allegro PCB Librarian XL and I have two questions. I really appreciate any help and guidance you could provide! QUESTION #1 :...
View ArticleForum Post: travel malang juanda dan sewa mobil di malang? pilih JAVA TRAVELINDO
Selamat datang di Java Travelindo! JAVA TRAVELINDO adalah perusahaan yang bergerak di bidang jasa tranportasi diantaranya adalah: travel malang juanda PP, Malang Surabaya PP, sewa mobil malang, paket...
View ArticleForum Post: Round off in VerilogA
How do I truncate a value in VerilogA ? I want to control the significant digits of a voltage value inside the VerilogA model. Please help me with this. Thanks. Regards, Aishwarya
View ArticleForum Post: RE: Footprint Viewer Not Present / Missing in OrCAD Capture 17.2
Not yet - raise an enhancement request with Cadence support or your Channel Partner. The more people that ask the better chance you have of getting something sooner. Reference the CCR number that...
View ArticleForum Post: RE: Setting all parameters in Allegro Xsection via Skill
It worked. Once again thanks.
View ArticleForum Post: RE: Round off in VerilogA
VerilogA has the ceil and floor functions - see the VerilogA reference documentation /doc/veriaref/veriaref.pdf Andrew
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